JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

Download PDF
ID 683298
Date 10/14/2022
Public
Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide x
1.1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example Quick Start Guide 1.2. Design Example Detailed Description 1.3. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives 1.4. Document Revision History for the JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
1.1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Design Example Parameters
1.1.4. Compiling and Testing the Design x
1.1.4.1. Board Connectivity 1.1.4.2. Hardware Test for System Console Control Design Example
1.2. Design Example Detailed Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Supported Configurations 1.2.4. Presets 1.2.5. Design Components 1.2.6. Clocking Scheme 1.2.7. Simulation 1.2.8. Design Example Files 1.2.9. Registers 1.2.10. Signals 1.2.11. Customizing the Design Example
1.2.5. Design Components x
1.2.5.1. Platform Designer System Component 1.2.5.2. Transport Layer 1.2.5.3. Test Pattern Generator 1.2.5.4. Test Pattern Checker
1.2.5.1. Platform Designer System Component x
1.2.5.1.1. JESD204B Subsystem in Platform Designer JESD204B IP Reset Sequencer Transceiver PHY Reset Controller Avalon® Memory-Mapped Bridge JESD204B Subsystem Address Map JTAG to Avalon® Master Bridge 1.2.5.1.2. Parallel I/O 1.2.5.1.3. ATX PLL 1.2.5.1.4. Core PLL 1.2.5.1.5. SPI Master
1.2.7. Simulation x
1.2.7.1. Testbench
1.2.11. Customizing the Design Example x
1.2.11.1. Modifying the JESD204B IP Core Parameters 1.2.11.2. Changing the Data Rate or Reference Clock Frequency
1. JESD204B Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

1.2.5.1.1. JESD204B Subsystem in Platform Designer

The JESD204B subsystem instantiates the following modules:

  • JESD204B Intel® FPGA IP
  • Reset sequencer
  • Transceiver PHY reset controller
  • Avalon® memory-mapped bridge

JESD204B IP

The generated design example is a self-contained system with its own JESD204B IP core instantiation that is separate from the IP core that is generated from the IP tab. The JESD204B IP base core and PHY layer connect to System Console through the Avalon® memory-mapped interconnect. The JESD204B IP core uses three separate Avalon® memory-mapped ports:

  • Base core TX data path—For dynamic reconfiguration of the TX CSR parameters
  • Base core RX data path—For dynamic reconfiguration of the RX CSR parameters
  • PHY layer—For dynamic reconfiguration of transceiver PHY CSR

You can dynamically change the configuration of the JESD204B IP core base and PHY layers through TCL scripts using the System Console.

The structure of the design example varies depending on the values of these JESD204B IP core parameters:

  • Data path:
    • Duplex—Both TX and RX data paths and CSR interfaces present
    • TX only—Only TX data path and CSR interface present
    • RX only—Only RX data path and CSR interface present
  • Transceiver dynamic reconfiguration mode:
    • When enabled, transceiver PHY reconfiguration interface is present in the design example and connected the JTAG to Avalon® master bridge (System Console control) module.
    • When disabled, transceiver PHY reconfiguration interface not present in design example.

Reset Sequencer

The reset sequencer is a standard Platform Designer component in the IP Catalog standard library. The reset sequencer generates the following system resets to reset various modules in the system:

  1. Core PLL reset—resets the core PLL
  2. Transceiver reset—resets the JESD204B IP core PHY module
  3. TX/RX JESD204B IP core CSR reset—resets the TX/RX JESD204B IP core CSRs
  4. TX/RX link reset—resets the TX/RX JESD204B IP core base module and transport layer
  5. TX/RX frame reset—resets the TX/RX transport layer, upstream and downstream modules

The reset sequencer has hard and soft reset options. The hard reset port connects to the global reset input pin in the top level design. The soft reset is activated via Avalon® memory-mapped interface by TCL scripts (System Console control). When you assert a hard or soft reset, the reset sequencer cycles through all the various module resets based on a pre-set sequence. The figure below illustrates the sequence and also shows how the reset sequencer output ports correspond to the modules that are being reset.

Figure 10. Reset Sequence


Transceiver PHY Reset Controller

The transceiver PHY reset controller is a standard Platform Designer component in the IP Catalog standard library. This module takes the transceiver PHY reset output from the reset sequencer and generates the proper analog and digital reset sequencing for the transceiver PHY module.

Avalon® Memory-Mapped Bridge

All the Avalon® memory-mapped submodules in the JESD204B subsystem are connected via Avalon® memory-mapped interconnect to a single Avalon® memory-mapped bridge. This bridge is the single interface for Avalon® memory-mapped communications into and out of the subsystem.

JESD204B Subsystem Address Map

Access the address map of the submodules in the JESD204B subsystem by clicking on the Address Map tab in the Platform Designer window.

Figure 11.  JESD204B Subsystem Address Map

JTAG to Avalon® Master Bridge

The JTAG to Avalon® master bridge is a standard Platform Designer component in the IP Catalog standard library. This module provides a connection between a host system and the Platform Designer system via the respective physical interfaces; JTAG on the host system end and Avalon® memory-mapped on the Platform Designer system end. Host systems can initiate Avalon® memory-mapped transactions by sending encoded streams of bytes via JTAG interface. The module supports reads and writes, but not burst transactions.

Related Information
Level Two Title