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Ixiasoft
A.1. Modify the Intel® Stratix® 10 SX SoC Development Kit to use a battery for the BBRAM
A.2. Modify the Intel® Stratix® 10 SX SoC Development Kit HPS DDR4 memory width and ECC configuration using the Golden Hardware Reference Design project
A.3. Safety and Regulatory Information
A.4. Compliance Information
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Ixiasoft
5.1. Preparing the Board
After successful FPGA configuration, with the power to the board off, follow these steps:
- Connect the USB cable to your PC and the Intel® FPGA Download Cable II port.
- Change SW1 and SW4 to the following configuration.
- Turn on power to the board and run the Board Test System.
Note: To ensure operating stability, keep the USB cable connected and the board powered on when running the demonstration application.
Bit 1 | Bit 2 | Bit 3 | Bit 4 | Bit 5 | Bit 6 | Bit 7 | Bit 8 |
---|---|---|---|---|---|---|---|
OFF | OFF | ON | ON | ON | ON | ON | ON |
Bit 1 | Bit 2 | Bit 3 | Bit 4 |
---|---|---|---|
ON | OFF | ON | ON |