Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 4/04/2022
Public

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18.1. About the Scaler

The Scaler Intel FPGA IP resizes the fields in an Intel FPGA streaming video compliant input to produce output fields of a different height and or width. The IP supports both full and lite variants of interface protocol. The scaler offers three algorithms for resizing images: nearest neighbor, bilinear and polyphase. The three algorithms offer three cost vs quality options. Nearest neighbor offers the lowest FPGA resource cost and the lowest output image quality and polyphase offers the highest quality at the highest cost.

The scaler can resize an incoming video field to produce an output field of any size, restricted only defined minimum and maximum widths and heights. You set the desired output field width and height at runtime via the register map (if the Avalon memory-mapped control agent interface is enabled), or via fixed parameters (if the Avalon memory-mapped control agent interface is not enabled). Full variants define the input field width and height by the image info packets received at the input interface. Lite variants define the input field width and height via the register map. With defined input and output widths and heights, the scaler applies the correct horizontal and vertical scaling ratios (which may be different).

The following bounds apply to the input and output field widths.

  • Input field width must be less than or equal to the value set in the maximum input field width parameter.
  • Output field width must be less than or equal to the value set in the maximum output field width parameter
  • Output field width must be greater than or equal to the value set in the number of pixels in parallel parameter

You may also choose to turn off scaling in the horizontal or vertical directions if either is not required. In this case, the output width or height will be unaltered, regardless of the settings in the register map. Also, the scaler only supports scaling for video with 4:4:4 chroma siting. Full variants assert the error flag for any of these restrictions.