Cyclone® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683375
Date 10/18/2023
Public
Document Table of Contents

8.5.3. CRC Calculation Time For Entire Device

While the CRC calculation is done on a per frame basis, it is important to know the time taken to complete CRC calculations for the entire device. The entire device detection time is the time taken to do CRC calculations on every frame in the device. This time depends on the device and the error detection clock frequency. The error detection clock frequency also depends on the device and on the internal oscillator frequency, which varies from 42.6 MHz to 100 MHz.

You can calculate the minimum and maximum time for any number of divisor based on the following formula:

Maximum time (n) = 2^(n-8) * tMAX

Minimum time (n) = 2^n / minimum divisor setting * tMIN

where the range of n is from 0 to 8.

Table 106.  Device EDCRC Detection Time in Cyclone® V DevicesThe following table lists the minimum and maximum time taken to calculate the CRC value:
  • The minimum time is derived using the maximum clock frequency with the minimum divisor factor (n) for each member code.
  • The maximum time is derived using the minimum clock frequency with the maximum divisor factor (n) of 8.
Variant Member Code tMIN (ms) tMAX (s) Minimum Divisor Settings
Cyclone V E A2 9 2.76 2
A4 9 2.76 2
A5 14 4.21 2
A7 12 7.36 1
A9 23 13.93 1
Cyclone V GX C3 12 1.83 4
C4 14 4.21 2
C5 14 4.21 2
C7 12 7.36 1
C9 23 13.93 1
Cyclone V GT D5 14 4.21 2
D7 12 7.36 1
D9 23 13.93 1
Cyclone V SE A2 14 4.21 2
A4 14 4.21 2
A5 12 7.36 1
A6 12 7.36 1
Cyclone V SX C2 14 4.21 2
C4 14 4.21 2
C5 12 7.36 1
C6 12 7.36 1
Cyclone V ST D5 12 7.36 1
D6 12 7.36 1