AN 669: Drive-On-Chip Design Example for Cyclone V Devices

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ID 683466
Date 5/15/2022
Public
Document Table of Contents
Document Table of Contents x
1. About the Drive-On-Chip Design Example for Cyclone V Devices 2. Motor Control Boards 3. Drive-On-Chip Design Example for Cyclone V Devices Features 4. Getting Started 5. Building the Design 6. Debugging and Monitoring the Drive-On-Chip Design Example with System Console 7. About the Scaling of Feedback Signals 8. Motor Control Software 9. Functional Description of the Drive-On-Chip Design Example 10. Achieving Timing Closure on a Motor Control Design 11. Design Security Recommendations 12. Reference Documents for the Drive-on-Chip Design Example 13. Document Revision History for AN 669: Drive-on-Chip Reference Design
4. Getting Started x
4.1. Software Requirements for the Drive-On-Chip Design Example for Cyclone V Devices 4.2. Downloading and Installing the Drive-On-Chip Design Example for Cyclone V Devices 4.3. Setting Up the Motor Control Board with your Development Board 4.4. Programming the Hardware onto the Device 4.5. Setting Up Terminal Emulator 4.6. Downloading the HPS Software to the Device
4.6. Downloading the HPS Software to the Device x
4.6.1. Downloading the HPS Software with the Arm GUI 4.6.2. Downloading the HPS Software with the Arm Script
5. Building the Design x
5.1. Compiling the Drive-on-Chip Design Example 5.2. Preparing the µC/OS-II HPS Software Files 5.3. Compiling the µC/OS-II HPS Software 5.4. Creating and Booting an HPS SD Card Software Image 5.5. Creating and Booting a SD Card with both Software Image and Hardware Image
5.3. Compiling the µC/OS-II HPS Software x
5.3.1. Compiling the µC/OS-II HPS Software with the Arm GUI 5.3.2. Compiling the µC/OS-II HPS Software with the Arm Script
6. Debugging and Monitoring the Drive-On-Chip Design Example with System Console x
6.1. System Console GUI Upper Pane for the Drive-On-Chip Design Example 6.2. System Console GUI Lower Pane for the Drive-On-Chip Design Example 6.3. Vibration Suppression Tab 6.4. Controlling the DC-DC Converter 6.5. Tuning the PI Controller Gains 6.6. Controlling the Speed and Position Demonstrations 6.7. Monitoring Performance
6.3. Vibration Suppression Tab x
6.3.1. About the Demonstration 6.3.2. Starting the Demonstration 6.3.3. FFT0 and FFT1 Graphs 6.3.4. Setting Up FFT 6.3.5. Setting Up Command Waveform 6.3.6. Setting Up Second Order IIR Filter
7. About the Scaling of Feedback Signals x
7.1. Signal Sensing in Sigma-Delta ADCs 7.2. Signal Scaling in the Software of the Drive-On-Chip Design Example 7.3. Scale Factors for the Drive-On-Chip Design Example in the System Console Toolkit
8. Motor Control Software x
8.1. Viewing Motor Control Software Help Files 8.2. Software Application Configuration Files 8.3. Defining a New Motor or Encoder Type 8.4. SoC HPS Motor Control Software Project 8.5. Building the HPS Preloader
9. Functional Description of the Drive-On-Chip Design Example x
9.1. Processor Subsystem 9.2. Six-channel PWM Interface 9.3. DC Link Monitor 9.4. Drive System Monitor 9.5. Quadrature Encoder Interface 9.6. Sigma-Delta ADC Interface for Drive Axes 9.7. DC-DC Converter 9.8. Motor Control Modes 9.9. FOC Subsystem 9.10. FFTs 9.11. DEKF Technique for Battery Management 9.12. Signals 9.13. Registers
9.4. Drive System Monitor x
9.4.1. Drive System Monitor States for the Drive-On-Chip Design Example
9.6. Sigma-Delta ADC Interface for Drive Axes x
9.6.1. Offset Adjustment for Sigma-Delta ADC Interface
9.7. DC-DC Converter x
9.7.1. DC-DC Control Simulink Models 9.7.2. Sigma-Delta ADC Interface for DC-DC Converter
9.7.1. DC-DC Control Simulink Models x
9.7.1.1. DC-DC Control Block 9.7.1.2. Generating VHDL for the DSP Builder for Intel FPGAs Models for the DC-DC Converter
9.7.1.1. DC-DC Control Block x
9.7.1.1.1. DC-DC Model and VHDL Entity Signal Names and Data Format
9.9. FOC Subsystem x
9.9.1. DSP Builder for Intel FPGAs Model for the Drive-On-Chip Designs 9.9.2. Avalon Memory-Mapped Interface 9.9.3. About DSP Builder for Intel FPGAs 9.9.4. DSP Builder for Intel FPGAs Folding 9.9.5. DSP Builder for Intel FPGAs Model Resource Usage 9.9.6. DSP Builder for Intel FPGAs Design Guidelines 9.9.7. Generating VHDL for the DSP Builder Models for the Drive-On-Chip Reference Designs
9.10. FFTs x
9.10.1. Servo FFTs 9.10.2. Vibration Suppression 9.10.3. Command Waveform 9.10.4. IIR Filter 9.10.5. IIR Filter Tuning Parameters 9.10.6. IIR Filter Examples 9.10.7. Vibration Detection
9.10.1. Servo FFTs x
9.10.1.1. Running test_servofft.mdl
10. Achieving Timing Closure on a Motor Control Design x
10.1. Optimizing Motor Control Designs
1. About the Drive-On-Chip Design Example for Cyclone V Devices
2. Motor Control Boards
3. Drive-On-Chip Design Example for Cyclone V Devices Features
4. Getting Started
5. Building the Design
6. Debugging and Monitoring the Drive-On-Chip Design Example with System Console
7. About the Scaling of Feedback Signals
8. Motor Control Software
9. Functional Description of the Drive-On-Chip Design Example
10. Achieving Timing Closure on a Motor Control Design
11. Design Security Recommendations
12. Reference Documents for the Drive-on-Chip Design Example
13. Document Revision History for AN 669: Drive-on-Chip Reference Design

5.5. Creating and Booting a SD Card with both Software Image and Hardware Image

You create a bootable SD card that contains both the software image and hardware image, so you can boot the software automatically without using the Arm Development Studio Debugger and you do not need to program the FPGA every single time.
  1. Create a bootable SD card image using the prebuilt image that the SoC EDS includes.
    1. On Windows, download and install an SD card image writing utility, for example balenaEtcher or win32diskimager.
    2. Find the bootable image for your development board.
      For the Cyclone SoC development board find CycloneV_Linux_SDCard .img in the Intel SoC EDS default installation directory: C:\intelFPGA\17.0\embedded\embeddedsw\socfpga\prebuilt_images\CycloneV_Linux_SDCard.tar.gz
    3. Launch SOC EDS Command Shell as an administrator, and change the current directory to the prebuilt_images directory by typing:
      cd ‘C:\intelFPGA\17.0\embedded\embeddedsw\socfpga\prebuilt_images’
    4. Untar the compressed image file by typing:.
      tar -xf CycloneV_Linux_SDCard.tar.gz
    5. Write the bootable image, CycloneV_Linux_SDCard.img, with your SD card image writing utility on Windows or dd command on Linux onto your SD card.
  2. Update the preloader with the binary image made from the Drive-On-Chip design.
    1. Type cd <project_dir>/software/spl_bsp in the SoC EDS command shell.
    2. Write the preloader image into the proper location in your SD card by typing:
      alt-boot-disk-util -p preloader-mkpimage.bin -a write -d <sdcard_drive_letter> .
      Where <sdcard_drive> is the drive your SD card appears as on your computer.
  3. On the Cyclone V SoC development board, set SW3 (MSEL) to ON-OFF-ON-OFF-ON (0:Up, 1:Down, 2:Up, 3:Down, 4:Up)
  4. Open a Nios II command window, go to <project_dir>\output_files by typing:
    cd <project_dir>\output_files
  5. Generate soc_system.rbf from DOC_TANDEM_CVSX.sof by typing this command in the Nios II command window.
    quartus_cpf -c -o bitstream_compression=on DOC_TANDEM_CVSX.sof soc_system.rbf
  6. Copy soc_system.rbf to the FAT partition on the SD card.
  7. Copy doc_tandem_cvsx.bin from the <project_dir>\software\DOC_TANDEM_CVSX to the FAT partition on the SD card.
  8. Enter U-boot
    1. Unmount the SD card from PC, then insert the SD card in the development board.
    2. Open your Terminal Emulator software and connect to the USB serial port on the development board.
    3. Apply power to the development board.
    4. Press a key in the terminal window when prompted, before the countdown finishes and the operating system boots.
  9. At the U-Boot prompt, edit the U-Boot environment variables and save them by typing:
    setenv fpgaconfig 'fatload mmc 0 $fpgadata $fpgarbffile; fpga load 0 $fpgadata $filesize; run bridge_enable_handoff'
    setenv fpgarbffile soc_system.rbf
    setenv docload 'fatload mmc 0 1000000 doc_tandem_cvsx.bin'
    setenv bootcmd 'run fpgaconfig; run docload; go 1000000'
    saveenv
  10. Power cycle the development board or reset by pushing Cold reset push button (S7). In the terminal window you will see the sequence: U-Boot starts to count down, then FPGA is configured and the DriveOnChip software is downloaded and started.
    Figure 5. Application starts-up
  11. Apply power to the power board when you see this message in terminal console
    ---> DC input voltage error - Check power connection.
    Figure 6. Application is ready for power board powered-up
The motor starts to turn.
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