AN 669: Drive-On-Chip Design Example for Cyclone V Devices

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ID 683466
Date 5/15/2022
Public
Document Table of Contents
Document Table of Contents x
1. About the Drive-On-Chip Design Example for Cyclone V Devices 2. Motor Control Boards 3. Drive-On-Chip Design Example for Cyclone V Devices Features 4. Getting Started 5. Building the Design 6. Debugging and Monitoring the Drive-On-Chip Design Example with System Console 7. About the Scaling of Feedback Signals 8. Motor Control Software 9. Functional Description of the Drive-On-Chip Design Example 10. Achieving Timing Closure on a Motor Control Design 11. Design Security Recommendations 12. Reference Documents for the Drive-on-Chip Design Example 13. Document Revision History for AN 669: Drive-on-Chip Reference Design
4. Getting Started x
4.1. Software Requirements for the Drive-On-Chip Design Example for Cyclone V Devices 4.2. Downloading and Installing the Drive-On-Chip Design Example for Cyclone V Devices 4.3. Setting Up the Motor Control Board with your Development Board 4.4. Programming the Hardware onto the Device 4.5. Setting Up Terminal Emulator 4.6. Downloading the HPS Software to the Device
4.6. Downloading the HPS Software to the Device x
4.6.1. Downloading the HPS Software with the Arm GUI 4.6.2. Downloading the HPS Software with the Arm Script
5. Building the Design x
5.1. Compiling the Drive-on-Chip Design Example 5.2. Preparing the µC/OS-II HPS Software Files 5.3. Compiling the µC/OS-II HPS Software 5.4. Creating and Booting an HPS SD Card Software Image 5.5. Creating and Booting a SD Card with both Software Image and Hardware Image
5.3. Compiling the µC/OS-II HPS Software x
5.3.1. Compiling the µC/OS-II HPS Software with the Arm GUI 5.3.2. Compiling the µC/OS-II HPS Software with the Arm Script
6. Debugging and Monitoring the Drive-On-Chip Design Example with System Console x
6.1. System Console GUI Upper Pane for the Drive-On-Chip Design Example 6.2. System Console GUI Lower Pane for the Drive-On-Chip Design Example 6.3. Vibration Suppression Tab 6.4. Controlling the DC-DC Converter 6.5. Tuning the PI Controller Gains 6.6. Controlling the Speed and Position Demonstrations 6.7. Monitoring Performance
6.3. Vibration Suppression Tab x
6.3.1. About the Demonstration 6.3.2. Starting the Demonstration 6.3.3. FFT0 and FFT1 Graphs 6.3.4. Setting Up FFT 6.3.5. Setting Up Command Waveform 6.3.6. Setting Up Second Order IIR Filter
7. About the Scaling of Feedback Signals x
7.1. Signal Sensing in Sigma-Delta ADCs 7.2. Signal Scaling in the Software of the Drive-On-Chip Design Example 7.3. Scale Factors for the Drive-On-Chip Design Example in the System Console Toolkit
8. Motor Control Software x
8.1. Viewing Motor Control Software Help Files 8.2. Software Application Configuration Files 8.3. Defining a New Motor or Encoder Type 8.4. SoC HPS Motor Control Software Project 8.5. Building the HPS Preloader
9. Functional Description of the Drive-On-Chip Design Example x
9.1. Processor Subsystem 9.2. Six-channel PWM Interface 9.3. DC Link Monitor 9.4. Drive System Monitor 9.5. Quadrature Encoder Interface 9.6. Sigma-Delta ADC Interface for Drive Axes 9.7. DC-DC Converter 9.8. Motor Control Modes 9.9. FOC Subsystem 9.10. FFTs 9.11. DEKF Technique for Battery Management 9.12. Signals 9.13. Registers
9.4. Drive System Monitor x
9.4.1. Drive System Monitor States for the Drive-On-Chip Design Example
9.6. Sigma-Delta ADC Interface for Drive Axes x
9.6.1. Offset Adjustment for Sigma-Delta ADC Interface
9.7. DC-DC Converter x
9.7.1. DC-DC Control Simulink Models 9.7.2. Sigma-Delta ADC Interface for DC-DC Converter
9.7.1. DC-DC Control Simulink Models x
9.7.1.1. DC-DC Control Block 9.7.1.2. Generating VHDL for the DSP Builder for Intel FPGAs Models for the DC-DC Converter
9.7.1.1. DC-DC Control Block x
9.7.1.1.1. DC-DC Model and VHDL Entity Signal Names and Data Format
9.9. FOC Subsystem x
9.9.1. DSP Builder for Intel FPGAs Model for the Drive-On-Chip Designs 9.9.2. Avalon Memory-Mapped Interface 9.9.3. About DSP Builder for Intel FPGAs 9.9.4. DSP Builder for Intel FPGAs Folding 9.9.5. DSP Builder for Intel FPGAs Model Resource Usage 9.9.6. DSP Builder for Intel FPGAs Design Guidelines 9.9.7. Generating VHDL for the DSP Builder Models for the Drive-On-Chip Reference Designs
9.10. FFTs x
9.10.1. Servo FFTs 9.10.2. Vibration Suppression 9.10.3. Command Waveform 9.10.4. IIR Filter 9.10.5. IIR Filter Tuning Parameters 9.10.6. IIR Filter Examples 9.10.7. Vibration Detection
9.10.1. Servo FFTs x
9.10.1.1. Running test_servofft.mdl
10. Achieving Timing Closure on a Motor Control Design x
10.1. Optimizing Motor Control Designs
1. About the Drive-On-Chip Design Example for Cyclone V Devices
2. Motor Control Boards
3. Drive-On-Chip Design Example for Cyclone V Devices Features
4. Getting Started
5. Building the Design
6. Debugging and Monitoring the Drive-On-Chip Design Example with System Console
7. About the Scaling of Feedback Signals
8. Motor Control Software
9. Functional Description of the Drive-On-Chip Design Example
10. Achieving Timing Closure on a Motor Control Design
11. Design Security Recommendations
12. Reference Documents for the Drive-on-Chip Design Example
13. Document Revision History for AN 669: Drive-on-Chip Reference Design

9.13. Registers

The Drive-on-Chip Design Example contains many registers that you can set.
Table 31.  Six-Channel PWM Interface Control and Status RegistersWrite reserved bits as zero and read as zero.
Address Name Bits Description Reset Value Access
0x00 - - Reserved - -

0x04

pwm_u

 [31:15] Reserved - -
[14:0] phase U PWM switching threshold in PWM clocks 0x0 RW

0x08

pwm_v

 [31:15] Reserved - -
[14:0] phase V PWM switching threshold threshold in PWM clocks 0x0 RW

0x0C

pwm_w

 [31:15] Reserved - -
[14:0] phase W PWM switching threshold threshold in PWM clocks 0x0 RW

0x10

max

 [31:15] Reserved - -
[14:0] PWM maximum count threshold in PWM clocks 0x0 RW

0x14

block

 [31:8] Reserved - -
[7:0] PWM blocking (dead time) register threshold in PWM clocks 0x0 RW

0x18

trigger_up

 [31:15] Reserved - -
[14:0] PWM up count trigger for ADC threshold in PWM clocks 0x0 RW

0x1C

trigger_down

 [31:15] Reserved - -
[14:0] PWM down count trigger for ADC threshold in PWM clocks 0x0 RW

0x20

gate

 [31:6] Reserved - -
[5] Phase U lower transistor gate signal 0x0 R
[4] Phase U upper transistor gate signal 0x0 R
[3] Phase V lower transistor gate signal 0x0 R
[2] Phase V upper transistor gate signal 0x0 R
[1] Phase W lower transistor gate signal 0x0 R
[0] Phase W upper transistor gate signal 0x0 R

0x24

carrier

 [31:16] Reserved - -
[15:0] PWM count value threshold in PWM clocks 0x0 R

0x28

multi_cycle

 [31:4] Reserved - -
[3:0] Cycles to skip for ADC sample strobes 0x0 RW

Table 32.  DC Link Monitor Interface Control and Status RegistersWrite reserved bits as zero and read as zero.
Address Name Bits Description Reset Value Access
0x00 - - Reserved - -
0x04 offset [31:16] Reserved - -
[15:0] Offset. A value of 16384 corresponds to a zero offset. 0x0 RW

0x08

 k_64 [31:1] Reserved - -
[0] sinc3 filter decimation rate. When set to 0, the sinc3 decimation rate is M=64; when set to 1, the sinc3 decimation rate is M=128. 0x0 RW

0x0C

 ref_disable [31:16] Reserved - -
[15:0] DC-link voltage disable level. This register provides the maximum allowable voltage for link voltage. If the maximum value is exceeded the overvoltage output is driven, to shut down the system. 0x0 RW

0x10

 link_ref [31:16] Reserved - -
[15:0] DC-link chopper voltage level. The chopper IGBT transistor is turned on when the DC-link voltage exceeds this value. 0x0 RW

0x14

 bottom_ref [31:16] Reserved - -
[15:0] DC-link undervoltage reference level. If the link voltage falls below the reference level the undervoltage output is driven. 0x0 RW

0x18

 brake_t [31:11] Reserved - -
[10:0] This register is not used. 0x0 RW

0x1C

 brake_max_level [31:16] Reserved - -
[15:0] This register is not used. 0x0 RW

0x20

 dc_link [31:16] Reserved - -
[15:0] Current link voltage reading 0x0 R
0x24 brake_level [31:16] Reserved - -
[15:0] This register is not used. 0x0 R

0x28

status

 [31:3] Reserved - -
[2] DC link overvoltage status 0x0 R
[1] DC link undervoltage status 0x0 R
[0] Chopper gate signal status 0x0 R
Table 33.  Drive System Monitor Control and Status RegistersWrite reserved bits as zero and read as zero. R/W1C bits are read, write a 1 to clear the bit
Address Name Bits Description Reset Value Access
0x00 control [31:3] Reserved - -
[2:0] Control. Write to this register to request a change of state in the drive system monitor. 0x0 RW
0x04 status [31:12] Reserved - -
[11:9] Current DSM state. 0x0 R
[8] PWM control, upper PWM enable - -
[7] PWM control, lower PWM enable 0x0 R
[6] PWM control, PWM enable - -
[4] IGBT error 0x0 R/W1C
[3] ADC clock status - R/W1C
[2] Undervoltage status 0x0 R/W1C
[1] Overvoltage status - R/W1C
[0] Overcurrent status 0x0 R/W1C
Table 34.  Quadrature Encoder Interface Control and Status RegistersWrite reserved bits as zero and read as zero.
Address Name Bits Description Reset Value Access
0x00 control [31:3] Reserved. - -
[2] direction bit. Reverses the count direction when set. 0x0 RW
[1] index_reset_en bit. Count will reset on index pulse if this bit is set. 0x0 RW
[0] index_capture_en bit. Count will be captured in index capture reg, when index pulse occurs, if this bit is set. 0x0 RW
0x04 count capture [31:0] Captures current count on each strobe. 0x0 R
0x08 maximum count [31:0] Maximum count. Count will reset to zero when it reaches this value. 0x3FFF RW
0x0C count [31:0] Current count value. 0x0 RW
0x10 index capture [31:0] Captures current count when index pulse occurs if index_capture_en bit is set. 0x0 R
Table 35.  Sigma-Delta ADC Interface Control and Status RegistersWrite reserved bits as zero and read as zero.
Address Name Bits Description Reset Value Access
0x0 - - Reserved - -
0x04 offset_u [31:16] Reserved. - -
[15:0] Offset for phase U. A value of 32,768 corresponds to 0 offset. 0x0 RW
0x08 offset_w [31:16] Reserved. - -
[15:0] Offset for phase W. A value of 32,768 corresponds to 0 offset. 0x0 RW
0x0C i_peak [31:10] Reserved. - -
[9:0] Overcurrent detection threshold. 0x0 RW
0x10 d [31:3] Reserved. - -
[2] sinc3 filter decimation rate. When set to 0, the sinc3 decimation rate is M=128 for the control loop and M=16 for overcurrent detection; when set to 1, the sinc3 decimation rate is M=64 for the control loop and M=8 for the overcurrent detection. 0x0 RW
[1] Overcurrent enable 0x0 RW
[0] Overvoltage enable 0x0 RW
0x14 irq_ack [31:1] Reserved. - -
[0] 0x0 W1C
0x18 status [31:5] Reserved. - -
[4] 0x0 R
[3] 0x0 R
[2] Overcurrent for phase U 0x0 R
[1] Overcurrent for phase W 0x0 R
[0] Overcurrent for any phase 0x0 R
0x1C i_u [31:10] Reserved. - -
[9:0] Current in phase U. 0x0 R
0x20 i_w [31:10] Reserved. - -
[9:0] Current in phase W. 0x0 R
0x24 i_peak [31:10] Reserved. - -
[9:0] Overcurrent detection threshold. 0x0 RW
0x28 i_v [31:10] Reserved. - -
[9:0] Current in phase V. 0x0 R
0x2C offset_v [31:16] Reserved. - -
[15:0] Offset for phase V. A value of 32,768 corresponds to 0 offset. 0x0 RW
0x2C Overcurrent_u [31:10] Reserved. - -
[9:0] Overcurrent value for phase U 0x0 R
0x2C Overcurrent_v [31:10] Reserved. - -
[9:0] Overcurrent value for phase V 0x0 R
0x2C Overcurrent_w [31:10] Reserved. - -
[9:0] Overcurrent value for phase W 0x0 R
Table 36.  DC-DC Converter Control and Status RegistersWrite reserved bits as zero and read as zero
Address Name Bits Description Reset Value Access

0x00

control

 [31:5] Reserved - -
[4] State of REGEN_EN signal from the power board - R
[3] Reserved - -
[2]

Enable regeneration

 0 RW
[1] Enable closed loop mode 0 RW
[0] Enable Dc-DC gated with enable_in input 0 RW

0x04

cmd_dc

 [31:14] Reserved - -
[13:0] Commanded DC-DC output level in 1V increments 0 RW

0x08

 fault_reg [31:6] Reserved - -
[5] Input overvoltage detected 0 RW
[4] Input undervoltage detected 0 RW
[3] Output overvoltage detected 0 RW
[2] Output undervoltage detected 0 RW
[1] Input overcurrent detected 0 RW
[0] Output overcurrent detected 0 RW
0x0C - - Reserved 0 -

0x10

duty

 [31:14] Reserved - -
[13:0] Duty cycle for open loop mode, 0 – 100 50 RW

0x14

freq

 [31:14] Reserved - -
[13:0] Frequency of operation, kHz 64 RW

0x18

-

 - Reserved - -

0x1C

 - - Reserved - -

0x20

fb_current_a

 [31:13] Reserved - -
[12:0] Phase 0 current feedback sample, 100 = 1A 0 RW

0x24

fb_current_b

 [31:13] Reserved - -
[12:0] Phase 1current feedback sample, 100 = 1A 0 RW

0x28

fb_voltage

 [31:13] Reserved - -
[12:0] DC-DC output voltage feedback sample, 40 = 1V 0 RW
0x2C - - Reserved 0 -
0x30 offset_fb_current_a [31:16] Reserved - -
[15:0] Phase 0 current feedback ADC offset 0x8000 RW
0x34 offset_fb_current_b [31:16] Reserved - -
[15:0] Phase 1 current feedback ADC offset 0x8000 RW
0x38 offset_fb_voltage [31:16] Reserved - -
[15:0] DC-DC output voltage feedback ADC offset 0x8000 RW
0x3C - - Reserved 0 -

0x40

pgain_voltage

 [31:14] Reserved - -
[13:0]

P gain coefficient for voltage control loop * 100

[AC TODO] resolution? Scale?

 300 RW

0x44

igain_voltage

 [31:14] Reserved - -
[13:0] I gain coefficient for voltage control loop * 1e-7 (1/avs_clk) 4000 RW

0x48

pgain_current

 [31:14] Reserved - -
[13:0] P gain coefficient for current control loop * 1000 20 RW

0x4C

igain_current

 [31:14] Reserved - -
[13:0] I gain coefficient for current control loop * V 25 RW
Table 37.  FFT IP RegistersWrite reserved bits as zero and read as zero. R/W1C bits are read, write a 1 to clear the bit
Address Name Bits Description Reset Value Access
0x00 busy [31:1] Reserved - -
[0] FFT data input Not ready, busy flag. 0x0 R
0x04 start [31:1] Reserved - -
[0] Start command. When write a new input data for FFT toggle this bit 0 to 1. 0x0 RW
0x40 SIZE_CFG [31:4] Reserved - -
[3:0] Power of 2 of FFT size. When set n, FFT size is 2^n. RW
0x80 D_input [31:16] Reserved - -
[15:0] Input data for FFT RW
Table 38.  FFT buffer memory RegistersWrite reserved bits as zero and read as zero. R/W1C bits are read, write a 1 to clear the bit
Address Name Bits Description ResetValue Access
0x0000 fft_result[0] [31:0] Real part of fft_result[0] 0 R
0x0004 fft_result[0] [31:0] Imaginary part of fft_result[0] 0 R
0x0008 fft_result[1] [31:0] Real part of fft_result[1] 0 R
0x000C fft_result[1] [31:0] Imaginary part of fft_result[1] 0 R
: :
0x7FF8 fft_result[4095] [31:0] Real part of fft_result[4095] 0 R
0x7FFC fft_result[4095] [31:0] Imaginary part of fft_result[4095] 0 R
Table 39.  FFT buffer Control and Status Registers

Write reserved bits as zero and read as zero. R/W1C bits are read, write a 1 to clear the bit
Address Name Bits Description Reset Value Access
0x0000 status [31:2] Reserved - -
[1] FFT IP busy. When 1, FFT IP is processing data. 0 R
[0] Data Ready. FFT buffer ready to read. When all FFT outputs are stored in the buffer, this bit set 1 by hardware. Software should set 0, when all buffer contents are read out. Only if this bit set 0, hardware starts writing FFT output to the buffer. 0 RW
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