AN 307: Intel® FPGA Design Flow for AMD* Xilinx* Users

ID 683562
Date 9/08/2023
Public

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4.3.2. Placement Constraints

The following table compares the most common AMD* Xilinx* placement constraints with the Intel® FPGA equivalent placement constraints:

Table 60.  Placement Constraints
AMD* Xilinx* Constraint Intel® FPGA Constraint Description
Assignment Name QSF Variable
PBLOCK Logic Lock Region CORE_ONLY_PLACE_REGION Specifies whether the placement region only applies to core logic.
FLOATING_REGION Specifies the type of floating region
PLACE_REGION Specifies the target and bounding boxes of a placement region
REGION_NAME Specifies the region name of a design instance.
RESERVE_PLACE_REGION Specifies whether the placement region prevents the Fitter from placing other logic in that region.
ROUTE_REGION Specifies the target and bounding boxes of a routing region.
PACKAGE_PIN <Pin Number> Location Assignment PIN_<Pin number> Assigns a location on the device for the current nodes or pins.
LOC (for primitive cell such as SLICE, RAMB) Location Assignment <Location> <Value> Assigns a location on the device for the current nodes or pins.
BEL (for registers, LUT, SRL, LUTRAM) Location Assignment <Location> <Value> Assigns a location on the device for the current nodes or pins.
PROHIBIT NA NA NA

To set or modify placement constraints, use the Intel® Quartus® Prime Assignment Editor. Alternatively, you can edit the .qsf file.