EPCQ-A Serial Configuration Device Datasheet

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ID 683818
Date 10/01/2019
Public
Document Table of Contents
Document Table of Contents x
1. EPCQ-A Serial Configuration Device Datasheet
1. EPCQ-A Serial Configuration Device Datasheet x
1.1. Supported Devices 1.2. Features 1.3. Operating Conditions 1.4. Pin Information 1.5. Device Package and Ordering Code 1.6. Memory Array Organization 1.7. Memory Operations 1.8. Status Register 1.9. Summary of Operation Codes 1.10. Power Mode 1.11. Timing Information 1.12. Programming and Configuration File Support 1.13. Appendix: SFDP Register Definitions 1.14. Document Revision History for the EPCQ-A Serial Configuration Device Datasheet
1.3. Operating Conditions x
1.3.1. Absolute Maximum Ratings 1.3.2. Recommended Operating Conditions 1.3.3. DC Operating Conditions 1.3.4. AC Measurement Conditions 1.3.5. ICC Supply Current 1.3.6. Capacitance
1.4. Pin Information x
1.4.1. Pin-Out Diagram for EPCQ4A, EPCQ16A and EPCQ32A Devices 1.4.2. Pin-Out Diagram for EPCQ64A and EPCQ128A Devices 1.4.3. EPCQ-A Device Pin Description
1.5. Device Package and Ordering Code x
1.5.1. Package 1.5.2. Ordering Code
1.6. Memory Array Organization x
1.6.1. Address Range for EPCQ4A 1.6.2. Address Range for EPCQ16A 1.6.3. Address Range for EPCQ32A 1.6.4. Address Range for EPCQ64A 1.6.5. Address Range for EPCQ128A
1.7. Memory Operations x
1.7.1. Timing Requirements
1.8. Status Register x
1.8.1. Read Status Operation 1.8.2. Write Status Operation
1.9. Summary of Operation Codes x
1.9.1. Read Bytes Operation (03h) 1.9.2. Fast Read Operation (0Bh) 1.9.3. Extended Dual Input Fast Read Operation (BBh) 1.9.4. Extended Quad Input Fast Read Operation (EBh) 1.9.5. Read Device Identification Operation (9Fh) 1.9.6. Read Silicon Identification Operation (ABh) 1.9.7. Write Enable Operation (06h) 1.9.8. Write Disable Operation (04h) 1.9.9. Write Bytes Operation (02h) 1.9.10. Quad Input Fast Write Bytes Operation (32h) 1.9.11. Erase Bulk Operation (C7h) 1.9.12. Erase Sector Operation (D8h) 1.9.13. Erase Subsector Operation (20h) 1.9.14. Read SFDP Register Operation (5Ah)
1.11. Timing Information x
1.11.1. Write Operation Timing 1.11.2. Read Operation Timing
1. EPCQ-A Serial Configuration Device Datasheet

1.8. Status Register

Table 16.  Status Register Bits
Bit R/W Default Value Name Value Description
7 R/W 0 5 Reserved
6 R/W 05 Reserved
5 R/W 0 TB (Top/Bottom Bit)
  • 1=Protected area starts from the bottom of the memory array.
  • 0=Protected area starts from the top of the memory array.
Determine that the protected area starts from the top or bottom of the memory array.
4 R/W 0 BP2 6 Table 17 through Table 21 list the protected area with reference to the block protect bits. Determine the area of the memory protected from being written or erased unintentionally.
3 R/W 0 BP16
2 R/W 0 BP06
1 R 0 WEL (Write Enable Latch Bit)
  • 1=Allows the following operation to run:
    • Write Bytes
    • Write Status Register
    • Erase Bulk
    • Erase Sector
  • 0=Rejects the above mentioned operations.
 Allows or rejects certain operation to run.
0 R 0 WIP (Write in Progress Bit)
  • 1=One of the following operation is in progress:
    • Write Status Register
    • Write Bytes
    • Erase
  • 0=no write or erase cycle in progress
 Indicates if there is a command in progress.

Section Content
Read Status Operation
Write Status Operation

5 Do not program these bits to 1.
6 The erase bulk and erase die operation is only available when all the block protect bits are set to 0. When any of the block protect bits are set to 1, the relevant area is protected from being written by a write bytes operation or erased by an erase sector operation.
Level Two Title