Intel® Cyclone® 10 LP FPGA Evaluation Kit User Guide

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ID 683580
Date 12/19/2019
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Evaluation Board Setup 4. Evaluation Board Components 5. Simple Socket Server 6. Board Test System A. Safety and Regulatory Information B. Additional Information
1. Overview x
1.1. Evaluation Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Board 1.4. Evaluation Board Revisions
1.1. Evaluation Kit Description x
1.1.1. Evaluation Board Description 1.1.2. Evaluation Kit Collateral 1.1.3. Power Supply Description
2. Getting Started x
2.1. Installing Quartus Prime Software 2.2. Installing the Evaluation Kit Collateral 2.3. Installing Intel® FPGA Download Cable Driver
3. Evaluation Board Setup x
3.1. Powering Up the Evaluation Board 3.2. Default Switch Settings 3.3. Recovering Factory Default Settings
4. Evaluation Board Components x
4.1. Board Overview 4.2. Intel® Cyclone® 10 LP FPGA Overview 4.3. MAX 10 System Controller Overview 4.4. FPGA Configuration 4.5. Status Elements 4.6. Setup Elements 4.7. General User Input/Output 4.8. Clocks 4.9. Connectors and Interfaces 4.10. Memory 4.11. System Power
4.4. FPGA Configuration x
4.4.1. Using the Quartus Prime Programmer 4.4.2. Program On-Board EPCQ or EPCQ-A Flash Memory 4.4.3. Active Serial Configuration
4.9. Connectors and Interfaces x
4.9.1. Gigabit Ethernet PHY 4.9.2. 2x20 GPIO Expansion Header 4.9.3. Arduino Connectors 4.9.4. Pmod Connectors
4.9.3. Arduino Connectors x
4.9.3.1. Digital IOs 4.9.3.2. Analog Inputs 4.9.3.3. Arduino Power
4.10. Memory x
4.10.1. HyperRAM 4.10.2. EPCQ or EPCQ-A Flash Memory
4.11. System Power x
4.11.1. Power Supply Options 4.11.2. Power Tree 4.11.3. Current Measurement
5. Simple Socket Server x
5.1. Connecting to the Simple Socket Server
6. Board Test System x
6.1. The Configure Menu 6.2. The System Info Tab 6.3. The GPIO Tab 6.4. The Flash Tab 6.5. The HyperRAM Tab 6.6. The Power Monitor 6.7. The Clock Control
A. Safety and Regulatory Information x
A.1. Safety Warnings A.2. Safety Cautions
B. Additional Information x
B.1. Revision History B.2. Compliance and Conformity Statements
1. Overview
2. Getting Started
3. Evaluation Board Setup
4. Evaluation Board Components
5. Simple Socket Server
6. Board Test System
A. Safety and Regulatory Information
B. Additional Information

4.9.3. Arduino Connectors

The Intel® Cyclone® 10 LP FPGA Evaluation Board features an Arduino UNO R3 type interface which is comprised of headers J4, J5, J6, J7, J18.

The header's location is compatible with Arduino UNO R3. This interface contains 17 digital IOs (include one Reset) and six Analog inputs.

The header's location and definition are shown in the figure below.

Figure 9. Arduino Connector
Table 17.  Arduino Connector
Board Reference Schematic Signal Name FPGA Pin Number I/O Standard Direction @ FPGA Description
Header 1 (PWR) J4.1 NC ---      
J4.2 IOREF --- --- --- Connected to VCC_3.3V
J4.3 ARDUINO_RSTn L3 3.3 V In Arduino Reset Input
J4.4 VCC_3.3V ---     3.3 V Power for Arduino shield
J4.5 VCC_5V_AR1       5 V Power for Arduino shield shared with VCC_5V
J4.6 GND        
J4.7 GND        
J4.8 NC       Reserve option to 5 V
Header 2 (Analog) J6.1 ARDUINO_ANA0 --- Analog In Arduino Analog Channel 0
J6.2 ARDUINO_ANA1 --- Analog In Arduino Analog Channel 1
J6.3 ARDUINO_ANA2 --- Analog In Arduino Analog Channel 2
J6.4 ARDUINO_ANA3 --- Analog In Arduino Analog Channel 3
J6.5 ARDUINO_ANA4 --- Analog In Arduino Analog Channel 4
J6.6 ARDUINO_ANA5 --- Analog In Arduino Analog Channel 5
Header 3 (Digital) J5.1 ARDUINO_IO8 K2 3.3 V IO Arduino Digital Bit 8
J5.2 ARDUINO_IO9 K5 3.3 V IO Arduino Digital Bit 9
J5.3 ARDUINO_IO10 L4 3.3 V IO Arduino Digital Bit 10
J5.4 ARDUINO_IO11 K1 3.3 V IO Arduino Digital 11
J5.5 ARDUINO_IO12 L2 3.3 V IO Arduino Digital 12
J5.6 ARDUINO_IO13 L1 3.3 V IO Arduino Digital 13
J5.7 GND --- GND --- ---
J5.8 ANA_VREF --- Analog In Arduino Analog Reference Voltage Reserved
J5.9 ARDUINO_SDA N2 3.3 V IO Arduino I2C Data
J5.10 ARDUINO_SCL N1 3.3 V IO Arduino I2C Clock
Header 4 (Digital) J7.1 ARDUINO_IO0 B1 3.3 V IO Arduino Digital Bit 0
J7.2 ARDUINO_IO1 C2 3.3 V IO Arduino Digital Bit 1
J7.3 ARDUINO_IO2 F3 3.3 V IO Arduino Digital Bit 2
J7.4 ARDUINO_IO3 D1 3.3 V IO Arduino Digital Bit 3
J7.5 ARDUINO_IO4 G2 3.3 V IO Arduino Digital Bit 4
J7.6 ARDUINO_IO5 G1 3.3 V IO Arduino Digital Bit 5
J7.7 ARDUINO_IO6 J2 3.3 V IO Arduino Digital Bit 6
J7.8 ARDUINO_IO7 J1 3.3 V IO Arduino Digital Bit 7
Header 5 (ICSP) J18.1 ARDUINO_IO12 L2 3.3 V IO Short to Arduino Digital Bit 12
J18.2 VCC_5V_AR2 --- --- --- 5 V Power for Arduino shield, shared with VCC_5v
J18.3 ARDUINO_IO13 L1 3.3 V IO Short to Arduino Digital Bit 13
J18.4 ARDUINO_IO11 K1 3.3 V IO Short to Arduino Digital Bit 11
J18.5 ARDUINO_RSTn L3 3.3 V In Short to Arduino Reset Input
J18.6 GND --- --- --- ---

Section Content
Digital IOs
Analog Inputs
Arduino Power

Level Two Title