CPRI Intel® FPGA IP User Guide

ID 683595
Date 4/04/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.20.1. CPRI Intel® FPGA IP Core Loopback Modes

Figure 67.  CPRI Intel® FPGA IP Core Loopback Modes


Table 48.  Loopback Modes
Tag in Figure Description How to Configure
1 External loopback: Use this configuration to test the full Tx and Rx paths from an application through the CPRI link and back to the application. Connect a CPRI REC master's CPRI Tx interface to its CPRI Rx interface by physically connecting the CPRI IP's high-speed transceiver output pins to its high-speed transceiver input pins.

The connection medium must support the data rate requirements of the CPRI IP.

For a CPRI RE slave, you must set tx_enable_force in L1_CONFIG.

2 Transceiver PMA serial forward loopback path is active. Turn on Enable transceiver PMA serial forward loopback path in the parameter editor and set the loop_forward field of the LOOPBACK register to the value 2'b01.
3 Active parallel loopback path does not exercise the transceiver. Turn on Enable parallel forward loopback paths in the parameter editor and set the loop_forward field of the LOOPBACK register to the value 2'b10 (to include the stitching logic to the transceiver) or 2'b11 (to exclude the stitching logic to the transceiver).
4 Reverse loopback path is active. Turn on Enable parallel reversed loopback paths in the parameter editor and set the loop_reversed field of the LOOPBACK register to a non-zero value. The register value specifies the parts of the CPRI frame that participate in the loopback path. Other parts of the CPRI frame are filled in from the local IP core.