CPRI Intel® FPGA IP User Guide

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ID 683595
Date 4/04/2022
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Document Table of Contents
Document Table of Contents x
1. About the CPRI Intel® FPGA IP Core 2. Getting Started with the CPRI Intel® FPGA IP Core 3. Functional Description 4. CPRI Intel® FPGA IP Core Signals 5. CPRI Intel® FPGA IP Core Registers A. Additional Information
1. About the CPRI Intel® FPGA IP Core x
1.1. CPRI Intel® FPGA IP Core Supported Features 1.2. CPRI Intel® FPGA IP Core Device Family and Speed Grade Support 1.3. Intel® FPGA IP Core Verification 1.4. Resource Utilization for CPRI Intel® FPGA IP Core 1.5. Release Information
1.2. CPRI Intel® FPGA IP Core Device Family and Speed Grade Support x
1.2.1. Device Family Support 1.2.2. CPRI Intel® FPGA IP Core Performance: Device and Transceiver Speed Grade Support
2. Getting Started with the CPRI Intel® FPGA IP Core x
2.1. Installation and Licensing 2.2. Generating CPRI Intel® FPGA IP Core 2.3. CPRI Intel® FPGA IP File Structure 2.4. CPRI Intel® FPGA IP Core Parameters 2.5. Integrating Your Intel® FPGA IP Core in Your Design: Required External Blocks 2.6. Simulating Intel FPGA IP Cores 2.7. Understanding the Testbench 2.8. Running the Design Example 2.9. Compiling the Full Design and Programming the FPGA
2.1. Installation and Licensing x
2.1.1. Intel® FPGA IP Evaluation Mode
2.5. Integrating Your Intel® FPGA IP Core in Your Design: Required External Blocks x
2.5.1. Adding the Transceiver TX PLL IP Core 2.5.2. Adding the Reset Controller 2.5.3. Adding the Transceiver Reconfiguration Controller 2.5.4. Adding the Off-Chip Clean-Up PLL 2.5.5. Adding and Connecting the Single-Trip Delay Calibration Blocks 2.5.6. Transceiver PLL Calibration 2.5.7. Reference and System PLL Clock for your IP Design
3. Functional Description x
3.1. Interfaces Overview 3.2. CPRI Intel® FPGA IP Core Clocking Structure 3.3. CPRI Intel® FPGA IP Core Reset Requirements 3.4. Start-Up Sequence Following Reset 3.5. AUX Interface 3.6. Direct IQ Interface 3.7. Ctrl_AxC Interface 3.8. Direct Vendor Specific Access Interface 3.9. Real-Time Vendor Specific Interface 3.10. Direct HDLC Serial Interface 3.11. Direct L1 Control and Status Interface 3.12. L1 Debug Interface 3.13. Media Independent Interface (MII) to External Ethernet Block 3.14. Gigabit Media Independent Interface (GMII) to External Ethernet Block 3.15. CPU Interface to CPRI Intel® FPGA IP Registers 3.16. Auto-Rate Negotiation 3.17. Extended Delay Measurement 3.18. Deterministic Latency and Delay Measurement and Calibration 3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces 3.20. Testing Features
3.2. CPRI Intel® FPGA IP Core Clocking Structure x
3.2.1. Example CPRI Intel® FPGA IP Core Clock Connections in Different Clocking Modes
3.4. Start-Up Sequence Following Reset x
3.4.1. Start-Up Sequence Interface Signals
3.5. AUX Interface x
3.5.1. AUX Interface Signals 3.5.2. AUX Interface Synchronization 3.5.3. Auxiliary Latency Cycles 3.5.4. Direct Interface CPRI Frame Data Format
3.15. CPU Interface to CPRI Intel® FPGA IP Registers x
3.15.1. CPU Interface Signals 3.15.2. Accessing the Hyperframe Control Words
3.15.2. Accessing the Hyperframe Control Words x
3.15.2.1. Specifying the Control Word 3.15.2.2. Specifying the Position in the Control Word 3.15.2.3. Retrieving the Hyperframe Control Words 3.15.2.4. Writing the Hyperframe Control Words
3.17. Extended Delay Measurement x
3.17.1. Extended Delay Measurement for Soft Internal Buffers 3.17.2. Extended Delay Measurement for Intel® Stratix® 10 Hard FIFOs 3.17.3. Extended Delay Measurement Interface
3.18. Deterministic Latency and Delay Measurement and Calibration x
3.18.1. Delay Measurement and Calibration Features 3.18.2. Delay Requirements 3.18.3. Single-Hop Delay Measurement 3.18.4. Multi-Hop Delay Measurement 3.18.5. Delay Calibration Features
3.18.3. Single-Hop Delay Measurement x
3.18.3.1. Rx Path Delay 3.18.3.2. Tx Path Delay 3.18.3.3. Round-Trip Delay
3.18.5. Delay Calibration Features x
3.18.5.1. Single-Trip Delay Calibration 3.18.5.2. Round-Trip Delay Calibration 3.18.5.3. Tx Bitslip Delay
3.18.5.1. Single-Trip Delay Calibration x
3.18.5.1.1. Single-Trip Latency Measurement and Calibration Interface Signals
3.19. CPRI Intel® FPGA IP Transceiver and Transceiver Management Interfaces x
3.19.1. CPRI Link 3.19.2. Main Transceiver Clock and Reset Signals 3.19.3. Arria V, Arria V GZ, Cyclone V, and Stratix V Transceiver Reconfiguration Interface 3.19.4. Intel® Arria® 10, Intel® Stratix® 10, and Intel® Agilex™ Transceiver Reconfiguration Interface 3.19.5. RS-FEC Interface 3.19.6. Interface to the External Reset Controller 3.19.7. Interface to the External PLL 3.19.8. Transceiver Debug Interface
3.20. Testing Features x
3.20.1. CPRI Intel® FPGA IP Core Loopback Modes 3.20.2. CPRI Intel® FPGA IP Core Self-Synchronization Feature
4. CPRI Intel® FPGA IP Core Signals x
4.1. CPRI Intel® FPGA IP Core L2 Interface 4.2. CPRI Intel® FPGA IP Core L1 Direct Access Interfaces 4.3. CPRI Intel® FPGA IP Core Management Interfaces 4.4. CPRI Intel® FPGA IP Core Transceiver and Transceiver Management Signals
5. CPRI Intel® FPGA IP Core Registers x
5.1. INTR Register 5.2. L1_STATUS Register 5.3. L1_CONFIG Register 5.4. BIT_RATE_CONFIG Register 5.5. PROT_VER Register 5.6. TX_SCR Register 5.7. RX_SCR Register 5.8. CM_CONFIG Register 5.9. CM_STATUS Register 5.10. START_UP_SEQ Register 5.11. START_UP_TIMER Register 5.12. FLSAR Register 5.13. CTRL_INDEX Register 5.14. TX_CTRL Register 5.15. RX_CTRL Register 5.16. RX_ERR Register 5.17. RX_BFN Register 5.18. LOOPBACK Register 5.19. TX_DELAY Register 5.20. RX_DELAY Register 5.21. TX_EX_DELAY Register 5.22. RX_EX_DELAY Register 5.23. ROUND_TRIP_DELAY Register 5.24. XCVR_BITSLIP Register 5.25. DELAY_CAL_STD_CTRL1 Register 5.26. DELAY_CAL_STD_CTRL2 Register 5.27. DELAY_CAL_STD_CTRL3 Register 5.28. DELAY_CAL_STD_CTRL4 Register 5.29. DELAY_CAL_STD_CTRL5 Register 5.30. DELAY_CAL_STD_STATUS Register 5.31. DELAY_CAL_RTD Register 5.32. XCVR_TX_FIFO_DELAY Register 5.33. XCVR_RX_FIFO_DELAY Register 5.34. IP_INFO Register 5.35. DEBUG_STATUS Register
A. Additional Information x
A.1. CPRI Intel® FPGA IP User Guide Archives A.2. Document Revision History for the CPRI Intel® FPGA IP User Guide
1. About the CPRI Intel® FPGA IP Core
2. Getting Started with the CPRI Intel® FPGA IP Core
3. Functional Description
4. CPRI Intel® FPGA IP Core Signals
5. CPRI Intel® FPGA IP Core Registers
A. Additional Information

5.24. XCVR_BITSLIP Register

Table 78.  XCVR_BITSLIP Register at Offset 0x5C
Bits Field Name Type Value on Reset Description
31:21 Reserved UR0 11'b0 —
20:16 rx_bitslip_out RO 5'b0 Number of bits of delay (bitslip) detected at the receiver word-aligner. Value can change at frame synchronization, when the transceiver is resetting. Any K28.5 symbol position change that occurs when word alignment is activated changes the bitslip value.
15:6 Reserved UR0 10'b0
5 tx_bitslip_en RW 1'b0 Enable manual tx_bitslip_in updates.
4:0 tx_bitslip_in RW 5'b0 Number of bits of delay (bitslip) the CPRI IP core adds at the CPRI Tx link.

The CPRI line bit rate determines the following maximum values for this field:

  • Maximum value for IP core variations with CPRI line bit rate 0.6144 Gbps: 9 bits.
  • Maximum value for IP core variations with CPRI line bit rate greater than 0.6144 Gbps: 19 bits.
Related Information
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