External Memory Interfaces Intel® Cyclone® 10 GX FPGA IP User Guide

ID 683663
Date 3/29/2021
Public

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4.1.1.20. cal_debug_out_reset_n for DDR3

User calibration debug clock domain reset interface

Table 28.  Interface: cal_debug_out_reset_nInterface type: Reset Output
Port Name Direction Description
cal_debug_out_reset_n Output Reset for the user clock connecting to the Avalon calibration debug_out bus. Asynchronous assertion and synchronous deassertion