External Memory Interfaces Intel® Cyclone® 10 GX FPGA IP User Guide

ID 683663
Date 3/29/2021
Public

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Document Table of Contents

12. Document Revision History for Intel® Cyclone® 10 GX External Memory Interfaces FPGA IP User Guide

Document Version Intel® Quartus® Prime Version IP Version Changes
2021.03.29 21.1 19.1.0
  • In the Simulating Memory IP chapter, removed references to the NCSim* simulator.
  • Added Package Migration topic to the Board Design Guidelines section of each protocol-specific chapter.
2019.09.30 19.3 19.1.0
  • Added the Release Information topic.
  • In the Intel® Cyclone® 10 GX EMIF IP for DDR3 chapter, changed the text of the third bullet in step 10, in the General Guidelines topic.
  • In the Intel® Cyclone® 10 GX EMIF IP Debugging chapter:
    • Restructured the Debugging Intel® Cyclone® 10 GX EMIF IP section.
    • Added the Using the Traffic Generator with the Generated Design Example topic.
  • Added the User Guide Archive chapter.
2019.04.01 19.1  
  • Added Slew Rates topic to the DDR3 Board Design Guidelines section of the DDR3 chapter.
  • Revised the Optimizing Timing topic in the Intel® Cyclone® 10 GX EMIF IP Timing Closure chapter.
2018.10.23 18.1   Removed inapplicable references to DDR4 from the Intel® Cyclone® 10 GX EMIF IP End-User Signals and Intel® Cyclone® 10 GX EMIF IP Debugging chapters.
2018.09.24 18.1  
  • Removed local_reset_req, local_reset_status, and hps_emif from all protocols in the Interface and Signal Descriptions section of the Intel® Cyclone® 10 GX EMIF IP End-User Signals chapter.
  • Removed mem_reset_n from the description of the mem interface for LPDDR3 in the Interface and Signal Descriptions section of the Intel® Cyclone® 10 GX EMIF IP End-User Signals chapter.
  • Removed a note from the I/O SSM Sharing topic, in the Product Architecture chapter.
  • Added notes to the Bank Management Efficiency and Data Transfer topics in the Optimizing Controller Performance chapter.
  • Added Efficiency Monitor and Protocol Checker section to the IP Debugging chapter.
  • Changed title from Intel® Cyclone® 10 External Memory Interfaces FPGA IP User Guide to Intel® Cyclone® 10 GX External Memory Interfaces FPGA IP User Guide.
2018.08.08 18.0  
  • In the Command and Address Signals topic in the DDR3 chapter, changed SSTL-12 I/O standard reference to 1.2V I/O standard.
  • Modified the descriptions of the Clock rate of user logic, Memory format, DQ width, and Enable In-System-Sources-and-Probes parameters in the DDR3 chapter.
  • Removed the Traffic Generator 2.0 section from the Intel® Cyclone® 10 EMIF IP Debugging chapter.
2018.05.07 18.0  
  • Changed document title from Intel® Cyclone® 10 External Memory Interfaces IP User Guide to External Memory Interfaces Intel® Cyclone® 10 FPGA IP User Guide.
  • In the Product Architecture chapter:
    • Revised the maximum speed rating for the Hard PHY in the EMIF Architecture: Introduction topic.
    • Added information to the first paragraph of the Input DQS Clock Tree topic.
    • Added information to the DQS Tracking topic.
  • In the Simulating Memory IP chapter:
    • Minor modifications to the Simulating Memory IP topic.
    • Removed note from Full calibration bullet point in the Simulation Options topic.
    • Minor modifications to the Simulation Walkthrough topic.
    • Changed directory path information in the Simulation Scripts, Functional Simulation with Verilog HDL, Functional Simulation with VHDL, and Simulating the Example Design topics.
  • In the DDR3 chapter:
    • Modified paragraph in the FPGA Resources topic.
    • Recast the second paragraph in the OCT topic.
    • Clarified the explanation of adjacent I/O banks in the Pin Guidelines for Intel® Cyclone® 10 EMIF IP topic.
    • Added explanation of adjacent I/O banks to the I/O Banks Selection section in the General Guidelines topic.
    • Modified equations in Guidelines for Calculating DDR3 Channel Signal Integrity topic.
  • In the LPDDR3 chapter:
    • Modified paragraph in the FPGA Resources topic.
    • Minor rewording of the second paragraph in the OCT topic.
    • Clarified the explanation of adjacent I/O banks in the Pin Guidelines for Intel® Cyclone® 10 EMIF IP topic.
    • Modified equations in Guidelines for Calculating LPDDR3 Channel Signal Integrity topic.
  • In the Timing Closure chapter:
    • Updated figures in the Read Capture Timing Analysis, Write Timing Analysis, Address and Command Timing Analysis, DQS Gating Timing Analysis, Write Leveling Timing Analysis, and Timing Report DDR topics.
  • In the Optimizing Controller Performance chapter:
    • Revised the calculations in the Refresh bullet point in the Interface Standard topic.
    • Revised the bulleted list of tools and methods in the Improving Controller Efficiency topic.
    • Revised the Frequency of Operation topic.
    • Added sentence to the beginning of the Command Reordering topic, explaining how to enable command reordering.
    • Revised the Bandwidth equation in the Bandwidth topic.
    • Updated figure in Additive Latency topic.
    • Updated both figures and associated text in Additive Latency and Bank Interleaving topic.
    • Removed the Command Queue Look Ahead Depth topic.
    • Added Enable Command Priority Control topic.
Table 162.  Document Revision History
Date Version Changes
November 2017 2017.11.06 Initial release.