Cyclone® V Device Overview

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ID 683694
Date 5/07/2018
Public
Document Table of Contents
Document Table of Contents x
Cyclone V Device Overview
Cyclone V Device Overview x
Key Advantages of Cyclone® V Devices Summary of Cyclone® V Features Cyclone® V Device Variants and Packages I/O Vertical Migration for Cyclone® V Devices Adaptive Logic Module Variable-Precision DSP Block Embedded Memory Blocks Clock Networks and PLL Clock Sources FPGA General Purpose I/O PCIe* Gen1 and Gen2 Hard IP External Memory Interface Low-Power Serial Transceivers SoC with HPS Dynamic Reconfiguration Enhanced Configuration and Configuration via Protocol Power Management Document Revision History for Cyclone® V Device Overview
Cyclone® V Device Variants and Packages x
Cyclone® V E Cyclone® V GX Cyclone® V GT Cyclone® V SE Cyclone® V SX Cyclone® V ST
Cyclone® V E x
Available Options Maximum Resources Package Plan
Cyclone® V GX x
Available Options Maximum Resources Package Plan
Cyclone® V GT x
Available Options Maximum Resources Package Plan
Cyclone® V SE x
Available Options Maximum Resources Package Plan
Cyclone® V SX x
Available Options Maximum Resources Package Plan
Cyclone® V ST x
Available Options Maximum Resources Package Plan
Embedded Memory Blocks x
Types of Embedded Memory Embedded Memory Capacity in Cyclone V Devices Embedded Memory Configurations
External Memory Interface x
Hard and Soft Memory Controllers External Memory Performance HPS External Memory Performance
Low-Power Serial Transceivers x
Transceiver Channels PMA Features PCS Features
SoC with HPS x
HPS Features FPGA Configuration and Processor Booting Hardware and Software Development
HPS Features x
System Peripherals and Debug Access Port HPS–FPGA AXI Bridges HPS SDRAM Controller Subsystem
Dynamic Reconfiguration x
Dynamic Reconfiguration Partial Reconfiguration
Cyclone V Device Overview

Clock Networks and PLL Clock Sources

550 MHz Cyclone® V devices have 16 global clock networks capable of up to operation. The clock network architecture is based on Intel® 's global, quadrant, and peripheral clock structure. This clock structure is supported by dedicated clock input pins and fractional PLLs.

Note: To reduce power consumption, the Intel® Quartus® Prime software identifies all unused sections of the clock network and powers them down.

PLL Features

The PLLs in the Cyclone® V devices support the following features:

  • Frequency synthesis
  • On-chip clock deskew
  • Jitter attenuation
  • Programmable output clock duty cycles
  • PLL cascading
  • Reference clock switchover
  • Programmable bandwidth
  • User-mode reconfiguration of PLLs
  • Low power mode for each fractional PLL
  • Dynamic phase shift
  • Direct, source synchronous, zero delay buffer, external feedback, and LVDS compensation modes

Fractional PLL

In addition to integer PLLs, the Cyclone® V devices use a fractional PLL architecture. The devices have up to eight PLLs, each with nine output counters. You can use the output counters to reduce PLL usage in two ways:

  • Reduce the number of oscillators that are required on your board by using fractional PLLs
  • Reduce the number of clock pins that are used in the device by synthesizing multiple clock frequencies from a single reference clock source

If you use the fractional PLL mode, you can use the PLLs for precision fractional-N frequency synthesis—removing the need for off-chip reference clock sources in your design.

The transceiver fractional PLLs that are not used by the transceiver I/Os can be used as general purpose fractional PLLs by the FPGA fabric.

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