Video and Vision Processing Suite Intel® FPGA IP User Guide

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ID 683329
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Plane Manager Intel® FPGA IP 21. Color Space Converter Intel® FPGA IP 22. Defective Pixel Correction Intel® FPGA IP 23. Deinterlacer Intel® FPGA IP 24. Demosaic Intel® FPGA IP 25. FIR Filter Intel® FPGA IP 26. Frame Cleaner Intel® FPGA IP 27. Full-Raster to Clocked Video Converter Intel® FPGA IP 28. Full-Raster to Streaming Converter Intel® FPGA IP 29. Genlock Controller Intel® FPGA IP 30. Generic Crosspoint Intel® FPGA IP 31. Genlock Signal Router Intel® FPGA IP 32. Guard Bands Intel® FPGA IP 33. Histogram Statistics Intel® FPGA IP 34. Interlacer Intel® FPGA IP 35. Mixer Intel® FPGA IP 36. Pixels in Parallel Converter Intel® FPGA IP 37. Scaler Intel® FPGA IP 38. Stream Cleaner Intel® FPGA IP 39. Switch Intel® FPGA IP 40. Tone Mapping Operator Intel® FPGA IP 41. Test Pattern Generator Intel® FPGA IP 42. Unsharp Mask Intel® FPGA IP 43. Video and Vision Monitor Intel FPGA IP 44. Video Frame Buffer Intel® FPGA IP 45. Video Frame Reader Intel FPGA IP 46. Video Frame Writer Intel FPGA IP 47. Video Streaming FIFO Intel® FPGA IP 48. Video Timing Generator Intel® FPGA IP 49. Vignette Correction Intel® FPGA IP 50. Warp Intel® FPGA IP 51. White Balance Correction Intel® FPGA IP 52. White Balance Statistics Intel® FPGA IP 53. Design Security 54. Document Revision History for Video and Vision Processing Suite User Guide
1. About the Video and Vision Processing Suite x
1.1. Video and Vision Processing IPs Features 1.2. Device Family Support 1.3. Video and Vision Processing IPs Release Information 1.4. Lite versus Full IP Variants 1.5. Glossary of Video and Vision Terminology
2. Getting Started with the Video and Vision Processing IPs x
2.1. Video and Vision Processing IP Evaluation Time-out Behavior 2.2. Generating a Video and Vision Processing IP 2.3. Simulating the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description x
3.1. Auxiliary Control Packets 3.2. Latency 3.3. IP Debugging Features 3.4. Stall Behavior and Error Recovery 3.5. Avalon Streaming Video Protocol Versus Intel FPGA Streaming Video Protocol
5. Video and Vision Processing IP Registers x
5.1. Video and Vision Processing IP Control Examples
7. Protocol Converter Intel® FPGA IP x
7.1. About the Protocol Converter IP 7.2. Protocol Converter IP Parameters 7.3. Protocol Converter IP Functional Description 7.4. Protocol Converter IP Interfaces 7.5. Protocol Converter IP Registers 7.6. Protocol Converter IP Software API
7.1. About the Protocol Converter IP x
7.1.1. Protocol Converter IP Performance and Resources
8. 1D LUT Intel® FPGA IP x
8.1. About the 1D LUT IP 8.2. 1D LUT IP Parameters 8.3. 1D LUT IP Interfaces 8.4. 1D LUT IP Registers 8.5. 1D LUT IP Software API
8.1. About the 1D LUT IP x
8.1.1. 1D LUT IP Performance and Resources
9. 3D LUT Intel® FPGA IP x
9.1. About the 3D LUT Intel® FPGA IP 9.2. 3D LUT IP Parameters 9.3. 3D LUT IP Block Description 9.4. 3D LUT IP Registers 9.5. 3D LUT IP Software API
9.1. About the 3D LUT Intel® FPGA IP x
9.1.1. 3D LUT IP Features 9.1.2. 3D LUT IP Performance IP and Resource Information
9.3. 3D LUT IP Block Description x
9.3.1. 3D LUT IP Interfaces 9.3.2. 3D LUT IP Latency
10. AXI-Stream Broadcaster Intel® FPGA IP x
10.1. About the AXI-Stream Broadcaster IP 10.2. AXI-Stream Broadcaster IP Parameters 10.3. AXI-Stream Broadcaster IP Interfaces
10.1. About the AXI-Stream Broadcaster IP x
10.1.1. AXI-Stream Broadcaster IP Features 10.1.2. AXI-Stream Broadcaster IP Performance and Resources
11. Bits per Color Sample Adapter Intel FPGA IP x
11.1. About the Bits per Color Sample Adapter IP 11.2. Bits per Color Sample Adapter IP Parameters 11.3. Bits per Color Sample Adapter IP Interfaces 11.4. Bits per Color Sample Adapter IP Registers 11.5. Bits per Color Sample Adapter Software API
11.1. About the Bits per Color Sample Adapter IP x
11.1.1. Bits per Color Sample Adapter IP Performance and Resources
12. Black Level Correction Intel® FPGA IP x
12.1. About the Black Level Correction IP 12.2. Black Level Correction IP Parameters 12.3. Black Level Correction IP Functional Description 12.4. Black Level Correction IP Registers 12.5. Black Level Correction IP Software API
12.1. About the Black Level Correction IP x
12.1.1. Black Level Correction IP Performance and Resources
12.3. Black Level Correction IP Functional Description x
12.3.1. Black Level Correction IP Interfaces
13. Black Level Statistics Intel® FPGA IP x
13.1. About the Black Level Statistics IP 13.2. Black Level Statistics IP Parameters 13.3. Black Level Statistics IP Interfaces 13.4. Black Level Statistics IP Registers 13.5. Black Level Statistics IP Software API
13.1. About the Black Level Statistics IP x
13.1.1. Black Level Statistics IP Performance and Resources
14. Chroma Key Intel® FPGA IP x
14.1. About the Chroma Key IP 14.2. Chroma Key IP Parameters 14.3. Chroma Key IP Interfaces 14.4. Chroma Key Replacement 14.5. Chroma Key IP Registers 14.6. Chroma Key IP Software API
14.1. About the Chroma Key IP x
14.1.1. Chroma Key IP Performance and Resources
15. Chroma Resampler Intel® FPGA IP x
15.1. About the Chroma Resampler IP 15.2. Chroma Resampler IP Parameters 15.3. Chroma Resampler IP Functional Description 15.4. Chroma Resampler IP Registers 15.5. Chroma Resampler IP Software API
15.1. About the Chroma Resampler IP x
15.1.1. Chroma Resampler Performance and Resources
15.3. Chroma Resampler IP Functional Description x
15.3.1. Chroma Resampler IP Interfaces
16. Clipper Intel® FPGA IP x
16.1. About the Clipper IP 16.2. Clipper IP Parameters 16.3. Clipper IP Interfaces 16.4. Clipper IP Registers 16.5. Clipper IP Software API
16.1. About the Clipper IP x
16.1.1. Clipper IP Performance and Resources
17. Clocked Video Input Intel® FPGA IP x
17.1. About the Clocked Video Input IP 17.2. Initializing the Clocked Video Input IP 17.3. Clocked Video Input IP Parameters 17.4. Clocked Video Input IP Interfaces 17.5. Clocked Video Input IP Registers 17.6. Clocked Video Input IP Software API
17.1. About the Clocked Video Input IP x
17.1.1. Clocked Video Input IP Features 17.1.2. Clocked Video Input IP Performance and Resources
18. Clocked Video to Full-Raster Converter Intel® FPGA IP x
18.1. About the Clocked Video to Full-Raster Converter IP 18.2. Clocked Video to Full-Raster Converter Parameters 18.3. Clocked Video to Full-Raster Converter Block Description 18.4. Clocked Video Converter to Full-Raster IP Registers
18.1. About the Clocked Video to Full-Raster Converter IP x
18.1.1. Clocked Video to Full-Raster Converter Features 18.1.2. Clocked Video to Full-Raster Converter Performance and Resources
18.3. Clocked Video to Full-Raster Converter Block Description x
18.3.1. Clocked Video to Full-Raster Converter Interfaces
19. Clocked Video Output Intel® FPGA IP x
19.1. About the Clocked Video Output IP 19.2. Clocked Video Output IP Parameters 19.3. Clocked Video Output IP Functional Description 19.4. Clocked Video Output IP Interfaces 19.5. Clocked Video Output IP Registers 19.6. Clocked Video Output IP Software API
19.1. About the Clocked Video Output IP x
19.1.1. Clocked Video Output IP Performance and Resources 19.1.2. Clocked Video Output IP Features
20. Color Plane Manager Intel® FPGA IP x
20.1. About the Color Plane Manager IP 20.2. Color Plane Manager IP Parameters 20.3. Color Plane Manager IP Functional Description 20.4. Color Plane Manager IP Registers 20.5. Color Plane Manager Software API
20.1. About the Color Plane Manager IP x
20.1.1. Color Plane Manager IP Performance and Resources
20.3. Color Plane Manager IP Functional Description x
20.3.1. Color Plane Manager IP Interfaces
21. Color Space Converter Intel® FPGA IP x
21.1. About the Color Space Converter IP 21.2. Color Space Converter IP Parameters 21.3. Color Space Converter IP Functional Description 21.4. Color Space Converter IP Registers 21.5. Color Space Converter IP Software API
21.1. About the Color Space Converter IP x
21.1.1. Color Space Converter IP Features 21.1.2. Color Space Converter IP Performance and Resources
21.3. Color Space Converter IP Functional Description x
21.3.1. Color Space Converter IP Interfaces
22. Defective Pixel Correction Intel® FPGA IP x
22.1. About the Defective Pixel Correction IP 22.2. Defective Pixel Correction IP Parameters 22.3. Defective Pixel Correction IP Functional Description 22.4. Defective Pixel Correction IP Registers 22.5. Defective Pixel Correction IP Software API
22.1. About the Defective Pixel Correction IP x
22.1.1. Defective Pixel Correction IP Performance and Resources
22.3. Defective Pixel Correction IP Functional Description x
22.3.1. Defective Pixel Correction IP Interfaces
23. Deinterlacer Intel® FPGA IP x
23.1. About the Deinterlacer IP 23.2. Deinterlacer Parameters 23.3. Deinterlacer Interfaces 23.4. Deinterlacer IP Registers 23.5. Deinterlacer IP Software API
23.1. About the Deinterlacer IP x
23.1.1. Deinterlacer Performance and Resources
24. Demosaic Intel® FPGA IP x
24.1. About the Demosaic IP 24.2. Demosaic IP Parameters 24.3. Demosaic IP Functional Description 24.4. Demosaic IP Registers 24.5. Demosaic IP Software API
24.1. About the Demosaic IP x
24.1.1. Demosaic IP Performance and Resources
24.3. Demosaic IP Functional Description x
24.3.1. Demosaic IP Interfaces
25. FIR Filter Intel® FPGA IP x
25.1. About the FIR Filter 25.2. FIR Filter Parameters 25.3. FIR Filter IP Operation 25.4. FIR Filter Interfaces 25.5. FIR Filter Registers 25.6. FIR Filter IP Software API
25.1. About the FIR Filter x
25.1.1. FIR Filter IP Performance and Resources
25.3. FIR Filter IP Operation x
25.3.1. FIR Filter Processing 25.3.2. FIR Filter Precision 25.3.3. FIR Coefficient Specification 25.3.4. FIR Filter Symmetry 25.3.5. Result to Output Data Type Conversion
25.3.4. FIR Filter Symmetry x
25.3.4.1. No Symmetry 25.3.4.2. Horizontal Symmetry 25.3.4.3. Vertical Symmetry 25.3.4.4. Horizontal and Vertical Symmetry 25.3.4.5. Diagonal Symmetry
26. Frame Cleaner Intel® FPGA IP x
26.1. About the Frame Cleaner IP 26.2. Frame Cleaner IP Parameters 26.3. Frame Cleaner IP Functional Description 26.4. Frame Cleaner IP Interfaces 26.5. Frame Cleaner IP Registers 26.6. Frame Cleaner IP Software API
26.1. About the Frame Cleaner IP x
26.1.1. Frame Cleaner IP Performance and Resources
27. Full-Raster to Clocked Video Converter Intel® FPGA IP x
27.1. About the Full-Raster to Clocked Video Converter 27.2. Full Raster to Clocked Video Converter Parameters 27.3. Full-Raster to Clocked Video Converter Block Description 27.4. Full-Raster to Clocked Video Converter Registers
27.1. About the Full-Raster to Clocked Video Converter x
27.1.1. Full-Raster to Clocked Video Converter Features 27.1.2. Full-Raster to Clocked Video Converter Performance and Resource Utilization
27.3. Full-Raster to Clocked Video Converter Block Description x
27.3.1. Full Raster to Clocked Video Converter Interfaces
28. Full-Raster to Streaming Converter Intel® FPGA IP x
28.1. About the Full-Raster to Streaming Converter IP 28.2. Full-Raster to Streaming Converter Parameters 28.3. Full-Raster to Streaming Converter Block Description
28.1. About the Full-Raster to Streaming Converter IP x
28.1.1. Full-Raster to Streaming Converter Features 28.1.2. Full-Raster to Streaming Converter Performance and Resources
28.3. Full-Raster to Streaming Converter Block Description x
28.3.1. Full-Raster to Streaming Converter Interfaces
29. Genlock Controller Intel® FPGA IP x
29.1. About the Genlock Controller IP 29.2. Genlock Controller IP Parameters 29.3. Genlock Controller IP Functional Description 29.4. Using Genlock Controller IP Software 29.5. Genlock Controller IP Registers 29.6. Genlock Controller IP Software API
29.1. About the Genlock Controller IP x
29.1.1. Genlock Controller IP Performance and Resources
29.3. Genlock Controller IP Functional Description x
29.3.1. Genlock Controller IP Interfaces
29.4. Using Genlock Controller IP Software x
29.4.1. Achieving Genlock Controller Free Running (for Initialization or from Lock to Reference Clock N) 29.4.2. Locking to Reference Clock N (from Genlock Controller IP free running) 29.4.3. Setting the VCXO hold over 29.4.4. Restarting the Genlock Controller IP 29.4.5. Locking to Reference Clock N New (from Locking to Reference Clock N Old) 29.4.6. Changing to Reference Clock or VCXO Base Frequencies (switch between p50 and p59.94 video formats and vice-versa) 29.4.7. Disturbing a Reference Clock (a cable pull)
30. Generic Crosspoint Intel® FPGA IP x
30.1. About the Generic Crosspoint IP 30.2. Generic Crosspoint IP Parameters 30.3. Generic Crosspoint IP Interfaces 30.4. Generic Crosspoint IP Registers 30.5. Generic Crosspoint IP Software API
30.1. About the Generic Crosspoint IP x
30.1.1. Generic Crosspoint IP Features 30.1.2. Generic Crosspoint Performance and Resources
31. Genlock Signal Router Intel® FPGA IP x
31.1. About the Genlock Signal Router IP 31.2. Genlock Signal Router IP Parameters 31.3. Genlock Signal Router IP Interfaces 31.4. Genlock Signal Router IP Registers 31.5. Genlock Signal Router IP Software API
31.1. About the Genlock Signal Router IP x
31.1.1. Genlock Signal Router IP Features 31.1.2. Genlock Signal Router IP Performance and Resources
32. Guard Bands Intel® FPGA IP x
32.1. About the Guard Bands IP 32.2. Guard Bands IP Parameters 32.3. Guard Bands IP Interfaces 32.4. Guard Bands IP Registers 32.5. Guard Bands IP Software API
32.1. About the Guard Bands IP x
32.1.1. Guard Bands IP Performance and Resources
33. Histogram Statistics Intel® FPGA IP x
33.1. About the Histogram Statistics IP 33.2. Histogram Statistics IP Parameters 33.3. Histogram Statistics IP Interfaces 33.4. Histogram Statistics IP Registers 33.5. Histogram Statistics IP Software API
33.1. About the Histogram Statistics IP x
33.1.1. Histogram Statistics IP Performance and Resources
34. Interlacer Intel® FPGA IP x
34.1. About the Interlacer IP 34.2. Interlacer IP Parameters 34.3. Interlacer IP Functional Description 34.4. Interlacer IP Registers 34.5. Interlacer IP Software API
34.1. About the Interlacer IP x
34.1.1. Interlacer IP Performance and Resources
34.3. Interlacer IP Functional Description x
34.3.1. Interlacer IP Interfaces
35. Mixer Intel® FPGA IP x
35.1. About the Mixer IP 35.2. Mixer IP Parameters 35.3. Mixer IP Functional Description 35.4. Mixer IP Registers 35.5. Mixer IP Software API
35.1. About the Mixer IP x
35.1.1. Mixer IP Performance and Resources
35.3. Mixer IP Functional Description x
35.3.1. Mixer IP Interfaces
36. Pixels in Parallel Converter Intel® FPGA IP x
36.1. About the Pixels in Parallel Converter IP 36.2. Pixels in Parallel Converter IP Parameters 36.3. Pixels in Parallel Converter Interfaces 36.4. Pixels in Parallel Converter Registers 36.5. Pixels in Parallel Converter IP Software API
36.1. About the Pixels in Parallel Converter IP x
36.1.1. Pixels in Parallel Converter IP Performance and Resources
37. Scaler Intel® FPGA IP x
37.1. About the Scaler 37.2. Scaler IP Parameters 37.3. Scaler IP Functional Description 37.4. Scaler IP Registers 37.5. Scaler IP Software API
37.1. About the Scaler x
37.1.1. Scaler IP Performance and Resources
37.2. Scaler IP Parameters x
37.2.1. Scaler Maximum Resolution
37.3. Scaler IP Functional Description x
37.3.1. Coefficient Selection 37.3.2. Coefficient Quantization 37.3.3. Filter Behavior at Edge Boundaries 37.3.4. Partial Frame Scaling 37.3.5. 422 and 420 Chroma Sampled Data Scaling 37.3.6. Scaler IP Interfaces
37.3.1. Coefficient Selection x
37.3.1.1. Updating Scaler IP Runtime Coefficients
38. Stream Cleaner Intel® FPGA IP x
38.1. About the Stream Cleaner IP 38.2. Stream Cleaner IP Parameters 38.3. Stream Cleaner IP Functional Description
38.1. About the Stream Cleaner IP x
38.1.1. Stream Cleaner IP Performance and Resources
38.3. Stream Cleaner IP Functional Description x
38.3.1. Stream Cleaner IP Interfaces
39. Switch Intel® FPGA IP x
39.1. About the Switch IP 39.2. Switch IP Parameters 39.3. Switch IP Functional Description 39.4. Switch IP Registers 39.5. Switch IP Software API
39.1. About the Switch IP x
39.1.1. Switch IP Performance and Resources
39.3. Switch IP Functional Description x
39.3.1. Switch IP Latency 39.3.2. Switch IP Interfaces
40. Tone Mapping Operator Intel® FPGA IP x
40.1. About the Tone Mapping Operator IP 40.2. TMO IP Parameters 40.3. TMO IP Block Description 40.4. TMO IP Registers 40.5. TMO IP Software API
40.1. About the Tone Mapping Operator IP x
40.1.1. TMO IP Features 40.1.2. TMO IP Performance and Resource Utilization
40.3. TMO IP Block Description x
40.3.1. TMO IP Interfaces 40.3.2. TMO IP Latency
41. Test Pattern Generator Intel® FPGA IP x
41.1. About the Test Pattern Generator IP 41.2. Test Pattern Generator IP Parameters 41.3. Test Pattern Generator IP Functional Description 41.4. Test Pattern Generator IP Registers 41.5. Test Pattern Generator IP Software API
41.1. About the Test Pattern Generator IP x
41.1.1. Test Pattern Generator IP Performance and Resources
41.3. Test Pattern Generator IP Functional Description x
41.3.1. Test Pattern Generator IP Interfaces
42. Unsharp Mask Intel® FPGA IP x
42.1. About the Unsharp Mask IP 42.2. Unsharp Mask IP Parameters 42.3. Unsharp Mask IP Functional Description 42.4. Unsharp Mask IP Registers 42.5. Unsharp Mask IP Software API
42.1. About the Unsharp Mask IP x
42.1.1. Unsharp Mask IP Performance and Resources
42.3. Unsharp Mask IP Functional Description x
42.3.1. Unsharp Mask IP Interfaces
43. Video and Vision Monitor Intel FPGA IP x
43.1. About the Video and Vision Monitor IP 43.2. Video and Vision Monitor IP Parameters 43.3. Video and Vision Monitor IP Functional Description 43.4. Video and Vision Monitor IP Registers 43.5. Video and Vision Monitor Software API
43.1. About the Video and Vision Monitor IP x
43.1.1. Video and Vision Monitor IP Performance and Resources
43.3. Video and Vision Monitor IP Functional Description x
43.3.1. Video and Vision Monitor IP Interfaces
44. Video Frame Buffer Intel® FPGA IP x
44.1. About the Video Frame Buffer IP 44.2. Video Frame Buffer IP Parameters 44.3. Video Frame Buffer IP Functional Description 44.4. Video Frame Buffer IP Registers 44.5. Video Frame Buffer IP Software API
44.1. About the Video Frame Buffer IP x
44.1.1. Video Frame Buffer Performance and Resources
44.3. Video Frame Buffer IP Functional Description x
44.3.1. Video Frame Buffer IP Interfaces
45. Video Frame Reader Intel FPGA IP x
45.1. About the Video Frame Reader IP 45.2. Video Frame Reader IP Parameters 45.3. Video Frame Reader IP Functional Description 45.4. Video Frame Reader IP Registers 45.5. Video Frame Reader IP Software API
45.1. About the Video Frame Reader IP x
45.1.1. Video Frame Reader IP Performance and Resources
45.3. Video Frame Reader IP Functional Description x
45.3.1. Video Frame Reader IP Interfaces
46. Video Frame Writer Intel FPGA IP x
46.1. About the Video Buffer Writer IP 46.2. Video Frame Writer IP Parameters 46.3. Video Frame Writer IP Functional Description 46.4. Video Frame Writer IP Registers 46.5. Video Frame Writer IP Software API
46.1. About the Video Buffer Writer IP x
46.1.1. Video Frame Writer IP Performance and Resources
46.3. Video Frame Writer IP Functional Description x
46.3.1. Video Frame Writer IP Interfaces
47. Video Streaming FIFO Intel® FPGA IP x
47.1. About the Video Streaming FIFO IP 47.2. Video Streaming FIFO IP Parameters 47.3. Video Streaming FIFO IP Interfaces
47.1. About the Video Streaming FIFO IP x
47.1.1. Video Streaming FIFO IP Performance and Resources
48. Video Timing Generator Intel® FPGA IP x
48.1. About the Video Timing Generator IP 48.2. Video Timing Generator IP Parameters 48.3. Video Timing Generator IP Functional Description 48.4. Video Timing Generator IP Interfaces 48.5. Video Timing Generator IP Registers 48.6. Video Timing Generator IP Software API
48.1. About the Video Timing Generator IP x
48.1.1. Video Timing Generator IP Features 48.1.2. Video Timing Generator IP Performance and Resources
49. Vignette Correction Intel® FPGA IP x
49.1. About the Vignette Correction IP 49.2. Vignette Correction IP Parameters 49.3. Vignette Correction IP Interfaces 49.4. Vignette Correction IP Registers 49.5. Vignette Correction IP Software API
49.1. About the Vignette Correction IP x
49.1.1. Vignette Correction IP Performance and Resources
50. Warp Intel® FPGA IP x
50.1. About the Warp IP 50.2. Warp IP Parameters 50.3. Warp IP Block Description 50.4. Warp IP Registers 50.5. Warp IP Software API
50.1. About the Warp IP x
50.1.1. Warp IP Features 50.1.2. Warp IP Performance and Resource Utilization
50.3. Warp IP Block Description x
50.3.1. Block Cache Tool 50.3.2. Warp IP Interfaces 50.3.3. Warp IP Latency 50.3.4. External Memory for Warp IP
50.5. Warp IP Software API x
50.5.1. Using Warp IP Software 50.5.2. Warp IP Software Code Examples
51. White Balance Correction Intel® FPGA IP x
51.1. About the White Balance Correction IP 51.2. White Balance Correction IP Parameters 51.3. White Balance Correction IP Functional Description 51.4. White Balance Correction IP Registers 51.5. White Balance Correction IP Software API
51.1. About the White Balance Correction IP x
51.1.1. White Balance Correction IP Performance and Resources
51.3. White Balance Correction IP Functional Description x
51.3.1. White Balance Correction IP Interfaces
52. White Balance Statistics Intel® FPGA IP x
52.1. About the White Balance Statistics IP 52.2. White Balance Statistics IP Parameters 52.3. White Balance Statistics IP Interfaces 52.4. White Balance Statistics IP Registers 52.5. White Balance Statistics IP Software API
52.1. About the White Balance Statistics IP x
52.1.1. White Balance Statistics IP Performance and Resources
53. Design Security x
53.1. Memory Subsystems 53.2. Considering Design Security
1. About the Video and Vision Processing Suite
2. Getting Started with the Video and Vision Processing IPs
3. Video and Vision Processing IPs Functional Description
4. Video and Vision Processing IP Interfaces
5. Video and Vision Processing IP Registers
6. Video and Vision Processing IPs Software Programming Model
7. Protocol Converter Intel® FPGA IP
8. 1D LUT Intel® FPGA IP
9. 3D LUT Intel® FPGA IP
10. AXI-Stream Broadcaster Intel® FPGA IP
11. Bits per Color Sample Adapter Intel FPGA IP
12. Black Level Correction Intel® FPGA IP
13. Black Level Statistics Intel® FPGA IP
14. Chroma Key Intel® FPGA IP
15. Chroma Resampler Intel® FPGA IP
16. Clipper Intel® FPGA IP
17. Clocked Video Input Intel® FPGA IP
18. Clocked Video to Full-Raster Converter Intel® FPGA IP
19. Clocked Video Output Intel® FPGA IP
20. Color Plane Manager Intel® FPGA IP
21. Color Space Converter Intel® FPGA IP
22. Defective Pixel Correction Intel® FPGA IP
23. Deinterlacer Intel® FPGA IP
24. Demosaic Intel® FPGA IP
25. FIR Filter Intel® FPGA IP
26. Frame Cleaner Intel® FPGA IP
27. Full-Raster to Clocked Video Converter Intel® FPGA IP
28. Full-Raster to Streaming Converter Intel® FPGA IP
29. Genlock Controller Intel® FPGA IP
30. Generic Crosspoint Intel® FPGA IP
31. Genlock Signal Router Intel® FPGA IP
32. Guard Bands Intel® FPGA IP
33. Histogram Statistics Intel® FPGA IP
34. Interlacer Intel® FPGA IP
35. Mixer Intel® FPGA IP
36. Pixels in Parallel Converter Intel® FPGA IP
37. Scaler Intel® FPGA IP
38. Stream Cleaner Intel® FPGA IP
39. Switch Intel® FPGA IP
40. Tone Mapping Operator Intel® FPGA IP
41. Test Pattern Generator Intel® FPGA IP
42. Unsharp Mask Intel® FPGA IP
43. Video and Vision Monitor Intel FPGA IP
44. Video Frame Buffer Intel® FPGA IP
45. Video Frame Reader Intel FPGA IP
46. Video Frame Writer Intel FPGA IP
47. Video Streaming FIFO Intel® FPGA IP
48. Video Timing Generator Intel® FPGA IP
49. Vignette Correction Intel® FPGA IP
50. Warp Intel® FPGA IP
51. White Balance Correction Intel® FPGA IP
52. White Balance Statistics Intel® FPGA IP
53. Design Security
54. Document Revision History for Video and Vision Processing Suite User Guide

46.5. Video Frame Writer IP Software API

The IP has a software driver for software control of the IP at run time. The IP does not fit any of the generic device models provided by the Nios II HAL. It exposes a set of dedicated accessors to the control and status registers. The driver structure inherits the base driver structure so all common methods described in Video and Vision Processing IPs Software API are applicable.

Register definition header file: intel_vvp_vfw_regs.h

Include file: intel_vvp_vfw.h

Table 910.  Video Frame Writer IP Software API
Name Description
intel_vvp_vfw_init Initialize the Frame Writer instance
intel_vvp_core_* Accessors defined in Video and Vision Processing IPs Software Programming Model . Writable when Lite is on. Readable when Lite is off and Debug features is on.
intel_vvp_vfw_get_lite_mode Returns if Lite mode is on
intel_vvp_vfw_get_debug_enabled Returns if Debug features is on
intel_vvp_vfw_get_max_height Returns the maximum supported height
intel_vvp_vfw_get_max_width Returns the maximum supported width
intel_vvp_vfw_get_bps Returns the number of bits per color sample
intel_vvp_vfw_get_number_of_color_planes Returns the number of color planes per pixel
intel_vvp_vfw_get_pixels_in_parallel Returns the number of pixels streamed in parallel
intel_vvp_vfw_get_mem_word_packing Returns the algorithm used for pixels packing in memory
intel_vvp_vfw_is_running Returns if the IP is currently processing video data
intel_vvp_vfw_get_commit_status Returns if there are uncommitted writes
intel_vvp_vfw_get_status Reads the status register
intel_vvp_vfw_is_buffer_available Returns if a field has been buffered to memory
intel_vvp_vfw_get_buffer_write_count Returns the number of fields written to memory
intel_vvp_vfw_get_buffer_start_addr Returns the base address in memory of the last buffer made available
intel_vvp_vfw_is_buffer_f1 Returns whether the field in the last buffer made available is a F1 field
intel_vvp_vfw_get_buffer_width Returns the field width for the last buffer made available
intel_vvp_vfw_get_buffer_height Returns the field height for the last buffer made available
intel_vvp_vfw_get_field_count Returns the field_count field extracted from the last image info packet (full variant only)
intel_vvp_vfw_acknowledge_buffer Acknowledges a newly written buffer
intel_vvp_vfw_set_run_mode Changes the run mode
intel_vvp_vfw_get_run_mode Returns the run mode
intel_vvp_vfw_set_num_buffers Sets the number of buffers in use
intel_vvp_vfw_get_num_buffers Returns the number of buffers in use
intel_vvp_vfw_set_base_addr Sets the base address for the first buffer in memory
intel_vvp_vfw_get_base_addr Returns the base address of the first buffer in memory
intel_vvp_vfw_set_inter_buffer_offset Sets the offset between field buffers in memory
intel_vvp_vfw_get_inter_buffer_offset Returns the offset between field buffers in memory
intel_vvp_vfw_set_inter_line_offset Sets the offset between lines in memory
intel_vvp_vfw_get_inter_line_offset Returns the offset between lines in memory
intel_vvp_vfw_set_irq_line_threshold Selects the line threshold used to fire the interrupt
intel_vvp_vfw_get_irq_line_threshold Returns the line threshold used to fire the interrupt
intel_vvp_vfw_overwrite_broken_fields Selects the overwrite behavior for broken fields
intel_vvp_vfw_get_overwrite_broken_fields Returns if broken fields are overwritten
intel_vvp_vfw_commit_writes Commit all outstanding writes

enum eIntelVvpVfwPacking

Members

kIntelVvpVfwPerfectPacking (0) - Perfect sample packing (no bits wasted)

kIntelVvpVfwColorPacking (1) - Color sample packing (color samples are not split across memory words)

kIntelVvpVfwPixelPacking (2) - Pixel packing (pixels are not split across memory words)

kIntelVvpVfwInvalidPacking (-1) - Invalid packing algorithm (used to indicate errors)

Description

Enumeration for the configurable sample packing in memory algorithms

enum eIntelVvpVfwRunMode

Members

kIntelVvpVfwStop (0) - Frame Writer is stopped

kIntelVvpVfwFreeRunning (1) - Frame Writer proceeds in a round-robin scheme using all available buffers

kIntelVvpVfwSingleShot (3) - Frame Writer proceeds and stops once all buffers have been written once

kIntelVvpVfwInvalidRunMode (-1) – Invalid value (used to indicate errors)

Description

Enumeration for the various write methods

intel_vvp_vfw_init

Prototype 
int intel_vvp_vfw_init(intel_vvp_vfw_instance *instance, intel_vvp_core_base base);
Description

Initializes a Frame Writer instance. The initialization stops early if the vendor ID or product ID read at the base address are not a match or if the register map version is not supported. Otherwise, the function proceeds to read and store the IP compile-time parameterization. The instance is not fully initialized and the application should not use it further if returning a non-zero error code.

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

base - base address of the register map

Returns

kIntelVvpCoreOk (0) in case of success, a negative error code in case of error

kIntelVvpCoreVidErr if the vendor id of the core is not the IntelFPGA vendor ID (0x6AF7).

kIntelVvpCorePidErr if the product_id does not match with the Frame Writer product ID

kIntelVvpCoreInstanceErr if the instance is a null pointer

kIntelVvpFrameWriterRegMapVersionErr if the register map is not supported

intel_vvp_vfw_get_lite_mode

Prototype 
bool intel_vvp_vfw_get_lite_mode(intel_vvp_vfw_instance *instance);
Description

Returns the value of the LITE_MODE register. The instance must be a valid intel_vvp_vfw_instance fully initialized

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

Returns

true if the IP is parameterized in lite mode

intel_vvp_vfw_get_debug_enabled

Prototype 
 bool intel_vvp_vfw_get_debug_enabled(intel_vvp_vfw_instance *instance);
Description

Returns the value of the DEBUG_ENABLED register. The instance must be a valid intel_vvp_vfw_instance fully initialized.

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

Returns

true if the IP is parameterized with debug features enabled

intel_vvp_vfw_get_max_height

Prototype 
 uint32_t intel_vvp_vfw_get_max_height(intel_vvp_vfw_instance *instance);
Description

Returns the value of the MAX_HEIGHT register. The instance must be a valid intel_vvp_vfw_instance fully initialized.

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

Returns

The maximum supported height set at configuration

intel_vvp_vfw_get_max_width

Prototype 
 uint32_t intel_vvp_vfw_get_max_width(intel_vvp_vfw_instance *instance);
Description

Returns the value of the MAX_WIDTH register. The instance must be a valid intel_vvp_vfw_instance fully initialized.

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

Returns

The maximum supported width set at configuration

intel_vvp_vfw_get_bps

Prototype 
 uint8_t intel_vvp_vfw_get_bps(intel_vvp_vfw_instance *instance);
Description

Returns the value of the BPS register. The instance must be a valid intel_vvp_vfw_instance fully initialized.

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

Returns

the number of bits per color sample selected at configuration

intel_vvp_vfw_get_number_of_color_planes

Prototype 
 uint8_t intel_vvp_vfw_get_number_of_color_planes(intel_vvp_vfw_instance *instance);
Description

Returns the value of the NUMBER_OF_COLOR_PLANES register. The instance must be a valid intel_vvp_vfw_instance fully initialized.

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

Returns

the number of color planes per pixel selected at configuration

intel_vvp_vfw_get_pixels_in_parallel

Prototype 
 uint8_t intel_vvp_vfw_get_pixels_in_parallel(intel_vvp_vfw_instance *instance);
Description

Returns the value of the PIXELS_IN_PARALLEL register. The instance must be a valid intel_vvp_vfw_instance fully initialized.

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

Returns

the number of pixels streamed in parallel selected at configuration

intel_vvp_vfw_get_mem_word_packing

Prototype 
 eIntelVvpVfwPacking intel_vvp_vfw_get_mem_word_packing(intel_vvp_vfw_instance *instance);
Description

Returns the value of the WORD_PACKING register. The instance must be a valid intel_vvp_vfw_instance fully initialized.

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

Returns

the algorithm used to pack/unpack pixels and color samples of a field in memory

intel_vvp_vfw_is_running

Prototype 
 bool intel_vvp_vfw_is_running(intel_vvp_vfw_instance* instance);
Description

Reads and returns the running bit of the STATUS register. The instance must be a valid intel_vvp_vfw_instance fully initialized.

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

Returns

True is the IP is currently reading a field, false when between two output fields

intel_vvp_vfw_get_commit_status

Prototype 
 bool intel_vvp_vfw_get_commit_status(intel_vvp_vfw_instance* instance);
Description

Reads and returns the commit status bit of the STATUS register. The instance must be a valid intel_vvp_vfw_instance fully initialized.

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

Returns

True is there are uncommitted writes

intel_vvp_vfw_get_status

Prototype 
 uint32_t intel_vvp_vfw_get_status(intel_vvp_vfw_instance* instance);
Description

Reads the STATUS register. The instance must be a valid intel_vvp_vfw_instance fully initialized.

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

Returns

The content of the STATUS register

intel_vvp_vfw_is_buffer_available

Prototype 
 bool intel_vvp_vfw_is_buffer_available(intel_vvp_vfw_instance* instance);
Description

Reads the BUFFER_AVAILABLE register. The instance must be a valid intel_vvp_vfw_instance fully initialized.

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

Returns

True if a new buffer has been written to memory since the last call to intel_vvp_vfw_acknowledge_buffer

intel_vvp_vfw_get_buffer_write_count

Prototype 
 uint32_t intel_vvp_vfw_get_buffer_write_count(intel_vvp_vfw_instance* instance);
Description

Reads the BUFFER_WRITE_COUNT register. The instance must be a valid intel_vvp_vfw_instance fully initialized.

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

Returns

The number of buffers written to memory that were not discarded

intel_vvp_vfw_get_buffer_start_addr

Prototype 
 uint32_t intel_vvp_vfw_get_buffer_start_addr(intel_vvp_vfw_instance* instance);
Description

Reads the BUFFER_START_ADDRESS register. The instance must be a valid intel_vvp_vfw_instance fully initialized.

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

Returns

The memory address for the last field flagged as available

intel_vvp_vfw_is_buffer_f1

Prototype 
 bool intel_vvp_vfw_is_buffer_f1(intel_vvp_vfw_instance* instance);
Description

Reads and returns the BUFFER_F1_FLAG register. The instance must be a valid intel_vvp_vfw_instance fully initialized.

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

Returns

True if the last buffer made available is a F1 field

intel_vvp_vfw_get_buffer_width

Prototype 
 uint32_t intel_vvp_vfw_get_buffer_width(intel_vvp_vfw_instance* instance);
Description

Reads and returns the BUFFER_WIDTH register. The instance must be a valid intel_vvp_vfw_instance fully initialized.

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

Returns

The width of the last buffer made available

intel_vvp_vfw_get_buffer_height

Prototype 
 uint32_t intel_vvp_vfw_get_buffer_height(intel_vvp_vfw_instance* instance);
Description

Reads and returns the BUFFER_HEIGHT register. The instance must be a valid intel_vvp_vfw_instance fully initialized.

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

Returns

The height of the last buffer made available

intel_vvp_vfw_get_field_count

Prototype 
 uint32_t intel_vvp_vfw_get_field_count(intel_vvp_vfw_instance* instance);
Description

Reads and returns the FIELD_COUNT register. The instance must be a valid intel_vvp_vfw_instance fully initialized and configured for full variant.

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

Returns

T

intel_vvp_vfw_acknowledge_buffer

Prototype 
 int intel_vvp_vfw_acknowledge_buffer(intel_vvp_vfw_instance *instance);
Description

Writes to the BUFFER_ACKNOWLEDGE register, freeing space for future buffers

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid

intel_vvp_vfw_set_run_mode

Prototype 
 int intel_vvp_vfw_set_run_mode(intel_vvp_vfw_instance *instance, eIntelVvpVfwRunMode run_mode);
Description

Writes a new value to the RUN_MODE register and chooses the write process used while storing buffers in memory

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

run_mode - the new run_mode

kIntelVvpVfwStop to stop the frame writer until another run-mode is selected

kIntelVvpVfwFreeRunning to store incoming fields using all buffers in round-robin fashion

kIntelVvpVfwSingleShot to store incoming fields until all buffers have been written once

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid

intel_vvp_vfw_get_run_mode

Prototype 
 eIntelVvpVfwRunMode intel_vvp_vfw_get_run_mode(intel_vvp_vfw_instance* instance);
Description

Reads and returns the current value of the RUN_MODE register. The instance must be a valid intel_vvp_vfw_instance fully initialized and configured to enable debug.

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

Returns

Last value written to the RUN_MODE register if the IP is configured to enable register read-back

intel_vvp_vfw_set_num_buffers

Prototype 
 int intel_vvp_vfw_set_num_buffers(intel_vvp_vfw_instance *instance, uint32_t num_buffers);
Description

Writes a new value to the NUM_BUFFERS register and selects the number of buffers

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

num_buffers - new number of buffers

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid

intel_vvp_vfw_get_num_buffers

Prototype 
 uint32_t intel_vvp_vfw_get_num_buffers(intel_vvp_vfw_instance* instance);
Description

Reads and returns the current value of the NUM_BUFFERS register. The instance must be a valid intel_vvp_vfw_instance fully initialized and configured to enable debug.

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

Returns

Last value written to the NUM_BUFFERS register if the IP is configured to enable register read-back

intel_vvp_vfw_set_base_addr

Prototype 
 int intel_vvp_vfw_set_base_addr(intel_vvp_vfw_instance *instance, uint32_t base_addr);
Description

Writes a new value to the BUFFER_BASE register and selects a new base address for buffers in memory

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

base_addr - the base address for the first buffer

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid

intel_vvp_vfw_get_base_addr

Prototype 
 uint32_t intel_vvp_vfw_get_base_addr(intel_vvp_vfw_instance* instance);
Description

Reads and returns the current value of the BUFFER_BASE register. The instance must be a valid intel_vvp_vfw_instance fully initialized and configured to enable debug.

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

Returns

Last value written to the BUFFER_BASE register if the IP is configured to enable register read-back

intel_vvp_vfw_set_inter_buffer_offset

Prototype 
 int intel_vvp_vfw_set_inter_buffer_offset(intel_vvp_vfw_instance *instance, uint32_t inter_buffer_offset);
Description

Writes a new value to the INTER_BUFFER_OFFSET register and selects a new inter-buffer offset for the buffers

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

inter_buffer_offset - the offset, in bytes, between two buffers, or, in other words, the number of bytes allocated to each buffer

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid

intel_vvp_vfw_get_inter_buffer_offset

Prototype 
 uint32_t intel_vvp_vfw_get_inter_buffer_offset(intel_vvp_vfw_instance* instance);
Description

Reads and returns the current value of the INTER_BUFFER_OFFSET register. The instance must be a valid intel_vvp_vfw_instance fully initialized and configured to enable debug.

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

Returns

Last value written to the INTER_BUFFER_OFFSET register if the IP is configured to enable register read-back

intel_vvp_vfw_set_inter_line_offset

Prototype 
 int intel_vvp_vfw_set_inter_line_offset(intel_vvp_vfw_instance *instance, uint32_t inter_line_offset);
Description

Writes a new value to the INTER_LINE_OFFSET register and selects a new inter-line offset for the buffers

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

inter_line_offset - the offset, in bytes, between consecutive lines

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid

intel_vvp_vfw_get_inter_line_offset

Prototype 
 uint32_t intel_vvp_vfw_get_inter_line_offset(intel_vvp_vfw_instance* instance);
Description

Reads and returns the current value of the INTER_LINE_OFFSET register. The instance must be a valid intel_vvp_vfw_instance fully initialized and configured to enable debug.

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

Returns

Last value written to the INTER_LINE_OFFSET register if the IP is configured to enable register read-back

intel_vvp_vfw_set_irq_line_threshold

Prototype 
 int intel_vvp_vfw_set_irq_line_threshold(intel_vvp_vfw_instance *instance, uint32_t line_threshold);
Description

Writes a new value to the IRQ_LINE_THRESHOLD register and selects a new threshold to fire the interrupt

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

line_threshold - the new line threshold

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid

intel_vvp_vfw_get_irq_line_threshold

Prototype 
 uint32_t intel_vvp_vfw_get_irq_line_threshold(intel_vvp_vfw_instance* instance);
Description

Reads and returns the current value of the IRQ_LINE_THRESHOLD register. The instance must be a valid intel_vvp_vfw_instance fully initialized and configured to enable debug.

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

Returns

Last value written to the IRQ_LINE_THRESHOLD register for the selected buffer set if the IP is configured to enable register read-back

intel_vvp_vfw_overwrite_broken_fields

Prototype 
 int intel_vvp_vfw_overwrite_broken_fields(intel_vvp_vfw_instance *instance, bool overwrite_broken);
Description

Writes a new value to the OVERWRITE_BROKEN register and selects how the Frame Writer handles broken fields

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

overwrite_broken - True to ignore and overwrite broken fields, false otherwise

Returns

kIntelVvpCoreOk for success, negative error code in case of failures

kIntelVvpCoreInstanceErr if the instance is invalid

intel_vvp_vfw_get_overwrite_broken_fields

Prototype 
 bool intel_vvp_vfw_get_overwrite_broken_fields(intel_vvp_vfw_instance* instance);
Description

Reads and returns the current value of the OVERWRITE_BROKEN register. The instance must be a valid intel_vvp_vfw_instance fully initialized and configured to enable debug.

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

Returns

Last value written to the OVERWRITE_BROKEN register if the IP is configured to enable register read-back

intel_vvp_vfw_commit_writes

Prototype 
 int intel_vvp_vfw_commit_writes(intel_vvp_vfw_instance* instance)
Description

Commits all pending writes before processing the next field. The instance must be valid.

Arguments

instance - pointer to the intel_vvp_vfw_instance software driver instance structure

Returns

kIntelVvpCoreOk (0) for success, negative error code otherwise

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