External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

ID 683741
Date 9/26/2022
Public

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4.1.5.16. cal_debug_reset_n for RLDRAM 3

User calibration debug clock domain reset interface

Table 154.  Interface: cal_debug_reset_nInterface type: Reset Input
Port Name Direction Description
cal_debug_reset_n Input Reset for the user clock connecting to the Avalon calibration debug bus. Asynchronous assertion and synchronous deassertion