Ethernet Subsystem Intel® FPGA IP User Guide

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ID 773413
Date 4/03/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Feature Description 3. Ethernet Subsystem Parameters 4. Subsystem IP Blocks 5. Interfaces and Signals 6. Recommended Clock Connections 7. Register Descriptions 8. Ethernet SS IP Example Design 9. Document Revision History for the Ethernet Subsystem Intel FPGA IP User Guide
1. Introduction x
1.1. Supported Features 1.2. Device Family Support 1.3. Release Information 1.4. Resource Utilization 1.5. Getting Started
2. Feature Description x
2.1. Ethernet Subsystem Intel FPGA IP Overview 2.2. Supported Features
3. Ethernet Subsystem Parameters x
3.1. Parameter Editor Parameters 3.2. E-Tile Port Enablement Guidelines and Restrictions 3.3. F-Tile Ethernet Port to PMA Channel Mapping
4. Subsystem IP Blocks x
4.1. AXI Stream Bridge 4.2. CSR Address Decoder 4.3. Subsystem Abstraction Layer (SAL) 4.4. Dynamic Reconfiguration Extension Subsystem 4.5. IEEE 1588v2 PTP 4.6. Auto-Negotation and Link Training 4.7. Priority Flow Control
4.3. Subsystem Abstraction Layer (SAL) x
4.3.1. Subsystem Abstraction Layer (SAL) Commands
4.3.1. Subsystem Abstraction Layer (SAL) Commands x
4.3.1.1. NOP(0x0) 4.3.1.2. get_hssi_profile for E-Tile 4.3.1.3. get_hssi_profile for F-Tile 4.3.1.4. set_hssi_profile for E-Tile 4.3.1.5. set_hssi_profile for F-Tile 4.3.1.6. read_MAC_statistic 4.3.1.7. get_mtu 4.3.1.8. set_csr for E-Tile 4.3.1.9. set_csr for F-Tile 4.3.1.10. get_csr for E-Tile 4.3.1.11. get_csr for F-Tile 4.3.1.12. enable_loopback for E-Tile 4.3.1.13. enable_loopback for F-Tile 4.3.1.14. disable_loopback for E-Tile 4.3.1.15. disable_loopback for F-Tile 4.3.1.16. Reset MAC Statistics 4.3.1.17. set_mtu for F-Tile 4.3.1.18. Ncsi_get_link_status 4.3.1.19. Reserved 4.3.1.20. firmware_version (0xFF)
4.5. IEEE 1588v2 PTP x
4.5.1. TX PTP Classifier
5. Interfaces and Signals x
5.1. AXI4 Interfaces 5.2. Serial Interface 5.3. Clocks 5.4. Resets
5.1. AXI4 Interfaces x
5.1.1. AXI-Lite CSR 5.1.2. AXI-ST Client Interface 5.1.3. AXI-ST PHY Direct 5.1.4. AXI-ST PTP 5.1.5. Flow Control
6. Recommended Clock Connections x
6.1. Driving Multiple Ports with the Same Clock 6.2. Clock Connections for MAC Async Client FIFO 6.3. F-Tile Clock Connections for PTP Synchronous and Asynchronous cases 6.4. Clock Connections for SyncE Operation on E-Tile 6.5. Clock Connections for SyncE Operation on F-Tile 6.6. F-Tile PMA and FEC Direct PHY IP Clock Output
7. Register Descriptions x
7.1. Subsystem Registers 7.2. Port Registers 7.3. F-Tile Address Maps 7.4. F-Tile ANLT Port Register Map 7.5. F-Tile PTP Tile Adapter Register Map 7.6. F-Tile DR Controller Register Map
7.1. Subsystem Registers x
7.1.1. Device Feature Header Lo 7.1.2. Device Feature Header Hi 7.1.3. Feature GUID_L 7.1.4. Feature GUID_H 7.1.5. Feature CSR ADDR 7.1.6. Feature CSR Size Group 7.1.7. Version 7.1.8. Feature List 7.1.9. Interface Attribute Port X Parameters 7.1.10. HSSI Command/Status 7.1.11. HSSI Control/Address 7.1.12. HSSI Read Data 7.1.13. HSSI Write Data 7.1.14. HSSI Ethernet Port X Status 7.1.15. Priority Flow Control 7.1.16. Priority Flow Control TX Queue Statistics 7.1.17. Priority Flow Control RX Queue Statistics 7.1.18. Priority Flow Control TX Queue Threshold 7.1.19. Priority Flow Control RX Queue Threshold 7.1.20. F-Tile DR Controller Status
7.2. Port Registers x
7.2.1. PTP Packet Classifier Registers
7.2.1. PTP Packet Classifier Registers x
7.2.1.1. Recognized and Unrecognized Packet Counters 7.2.1.2. Parse Graph Specific Packet Counters
8. Ethernet SS IP Example Design x
8.1. Steps to Generate the Example Design 8.2. Supported Simulators 8.3. Running the Simulation Tests 8.4. Running the Hardware Tests
8.3. Running the Simulation Tests x
8.3.1. Steps to Simulate the Design Example
8.4. Running the Hardware Tests x
8.4.1. Supported Boards 8.4.2. Steps to Compile the Design Example for Hardware 8.4.3. Steps to Run the Design Example on Hardware
8.4.2. Steps to Compile the Design Example for Hardware x
8.4.2.1. Steps to generate Routing Delay for PTP Enabled Designs
1. Introduction
2. Feature Description
3. Ethernet Subsystem Parameters
4. Subsystem IP Blocks
5. Interfaces and Signals
6. Recommended Clock Connections
7. Register Descriptions
8. Ethernet SS IP Example Design
9. Document Revision History for the Ethernet Subsystem Intel FPGA IP User Guide

5.1.4. AXI-ST PTP

The AXI-ST PTP Interface is available when PTP feature is enabled for the user selected subsystem Profile.
Table 33.  AXI-ST Tx ToD Interface Signals
Signal Name Direction Type Description
p<n>_app_ss_st_txtod_tvalid In Control Data valid signal.
p<n>_app_ss_st_txtod_tdata[95:0] In Data

Time-of Day according to the Local Clock for TX data path.

This bus is used to present the current time of day (according to the local clock) to the TX data path of the Ethernet core.

The format of the time is IEEE 1588v2 (96 bits).

[95:48]:Seconds

[47:16]:Nanoseconds

[15:0]:Fractional nanoseconds

Table 34.  AXI-Rx ToD Interface Signals
Signal Name Direction Type Description
p<n>_app_ss_st_rxtod_tvalid In Control Datavalid signal.
p<n>_app_ss_st_rxtod_tdata[95:0] In Data

Time-of Day according to the Local Clock for the TX data path.

This bus is used to present the current time of day (according to the local clock) to the TX data path of Ethernet Core.

The format of the time is IEEE 1588v2 (96 bits)

[95:48]:Seconds

[47:16]:Nanoseconds

[15:0]:Fractional nanoseconds.

Table 35.  AXI-ST Tx Egress Timestamp 0 Interface Signals
Signal Name Direction Type Description
p<n>_ss_app_st_txegrts0_tvalid Out Control TXEgress Timestamp valid signal.
p<n>_ss_app_st_txegrts0_tdata[103:0] Out Data

bits [103:96] - o_ptp_ets_fp[7:0]:TX Egress Timestamp Fingerprint.

bits [95:0] - o_ptp_ets[95:0]:TXEgress Timestamp.

[95:48]:Seconds.

[47:16]:Nanoseconds.

[15:0]:Fractional nanoseconds.

Table 36.  AXI-ST Tx Egress Timestamp 1 Interface SignalsThe AXI-ST Tx Egress Timestamp 1 Interface Signals only exist on F-tile.
Signal Name Direction Type Description
p{0..15}_ss_app_st_txegrts1_tvalid Out Control

Valid. Asserted when internal signal o_ptp_ets_valid[1:1] asserted.

o_ptp_ets_valid[1:1] - TX Egress Timestamp Valid when rate is 400G
p{0..15}_ss_app_st_txegrts1_tdata Out Data

Data.

[<w>+96:96] - o_ptp_ets_fp[<w>*2-1:w] (TX Egress Timestamp Fingerprint when rate is 400G)

[95:0] - o_ptp_ets[191:96] (TX Egress Timestamp when rate is 400G)

* w is set to 8 by default. If w is configured to more than 8 (maximum 32 in F-tile, 8 in E-tile)
Table 37.  AXI-ST Rx Ingress Timestamp 0 Interface Signals
Signal Name Direction Type Description
p<n>_ss_app_st_rxingrts0_tvalid Out Control RXingress Timestamp valid signal.
p<n>_ss_app_st_rxingrts0_tdata[95:0]

Out

 Data

o_ptp_rx_its[95:0]:

Ingress RX timestamp signal.

[95:48]:Seconds

[47:16]:Nanoseconds

[15:0]:Fractional nanoseconds

Table 38.  AXI-ST Rx Ingress Timestamp 1 Interface SignalsThe AXI-ST Rx Ingress Timestamp 1 Interface Signals only exist on F-tile.
Signal Name Direction Type Description
p{0..15}_ss_app_st_rxingrts1_tvalid Out Control

Valid. Asserted when internal signal o_ptp_rx_its_valid [1:1] asserted.

o_ptp_rx_its_valid[1:1] - RX Ingress Timestamp Valid when rate is 400G
p{0..15}_ss_app_st_rxingrts1_tdata [95:0] Out Data

Data.

[95:0] - o_ptp_rx_its[181:96] (TR Egress Timestamp when rate is 400G
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