Ethernet Subsystem Intel® FPGA IP User Guide

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ID 773413
Date 4/03/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Feature Description 3. Ethernet Subsystem Parameters 4. Subsystem IP Blocks 5. Interfaces and Signals 6. Recommended Clock Connections 7. Register Descriptions 8. Ethernet SS IP Example Design 9. Document Revision History for the Ethernet Subsystem Intel FPGA IP User Guide
1. Introduction x
1.1. Supported Features 1.2. Device Family Support 1.3. Release Information 1.4. Resource Utilization 1.5. Getting Started
2. Feature Description x
2.1. Ethernet Subsystem Intel FPGA IP Overview 2.2. Supported Features
3. Ethernet Subsystem Parameters x
3.1. Parameter Editor Parameters 3.2. E-Tile Port Enablement Guidelines and Restrictions 3.3. F-Tile Ethernet Port to PMA Channel Mapping
4. Subsystem IP Blocks x
4.1. AXI Stream Bridge 4.2. CSR Address Decoder 4.3. Subsystem Abstraction Layer (SAL) 4.4. Dynamic Reconfiguration Extension Subsystem 4.5. IEEE 1588v2 PTP 4.6. Auto-Negotation and Link Training 4.7. Priority Flow Control
4.3. Subsystem Abstraction Layer (SAL) x
4.3.1. Subsystem Abstraction Layer (SAL) Commands
4.3.1. Subsystem Abstraction Layer (SAL) Commands x
4.3.1.1. NOP(0x0) 4.3.1.2. get_hssi_profile for E-Tile 4.3.1.3. get_hssi_profile for F-Tile 4.3.1.4. set_hssi_profile for E-Tile 4.3.1.5. set_hssi_profile for F-Tile 4.3.1.6. read_MAC_statistic 4.3.1.7. get_mtu 4.3.1.8. set_csr for E-Tile 4.3.1.9. set_csr for F-Tile 4.3.1.10. get_csr for E-Tile 4.3.1.11. get_csr for F-Tile 4.3.1.12. enable_loopback for E-Tile 4.3.1.13. enable_loopback for F-Tile 4.3.1.14. disable_loopback for E-Tile 4.3.1.15. disable_loopback for F-Tile 4.3.1.16. Reset MAC Statistics 4.3.1.17. set_mtu for F-Tile 4.3.1.18. Ncsi_get_link_status 4.3.1.19. Reserved 4.3.1.20. firmware_version (0xFF)
4.5. IEEE 1588v2 PTP x
4.5.1. TX PTP Classifier
5. Interfaces and Signals x
5.1. AXI4 Interfaces 5.2. Serial Interface 5.3. Clocks 5.4. Resets
5.1. AXI4 Interfaces x
5.1.1. AXI-Lite CSR 5.1.2. AXI-ST Client Interface 5.1.3. AXI-ST PHY Direct 5.1.4. AXI-ST PTP 5.1.5. Flow Control
6. Recommended Clock Connections x
6.1. Driving Multiple Ports with the Same Clock 6.2. Clock Connections for MAC Async Client FIFO 6.3. F-Tile Clock Connections for PTP Synchronous and Asynchronous cases 6.4. Clock Connections for SyncE Operation on E-Tile 6.5. Clock Connections for SyncE Operation on F-Tile 6.6. F-Tile PMA and FEC Direct PHY IP Clock Output
7. Register Descriptions x
7.1. Subsystem Registers 7.2. Port Registers 7.3. F-Tile Address Maps 7.4. F-Tile ANLT Port Register Map 7.5. F-Tile PTP Tile Adapter Register Map 7.6. F-Tile DR Controller Register Map
7.1. Subsystem Registers x
7.1.1. Device Feature Header Lo 7.1.2. Device Feature Header Hi 7.1.3. Feature GUID_L 7.1.4. Feature GUID_H 7.1.5. Feature CSR ADDR 7.1.6. Feature CSR Size Group 7.1.7. Version 7.1.8. Feature List 7.1.9. Interface Attribute Port X Parameters 7.1.10. HSSI Command/Status 7.1.11. HSSI Control/Address 7.1.12. HSSI Read Data 7.1.13. HSSI Write Data 7.1.14. HSSI Ethernet Port X Status 7.1.15. Priority Flow Control 7.1.16. Priority Flow Control TX Queue Statistics 7.1.17. Priority Flow Control RX Queue Statistics 7.1.18. Priority Flow Control TX Queue Threshold 7.1.19. Priority Flow Control RX Queue Threshold 7.1.20. F-Tile DR Controller Status
7.2. Port Registers x
7.2.1. PTP Packet Classifier Registers
7.2.1. PTP Packet Classifier Registers x
7.2.1.1. Recognized and Unrecognized Packet Counters 7.2.1.2. Parse Graph Specific Packet Counters
8. Ethernet SS IP Example Design x
8.1. Steps to Generate the Example Design 8.2. Supported Simulators 8.3. Running the Simulation Tests 8.4. Running the Hardware Tests
8.3. Running the Simulation Tests x
8.3.1. Steps to Simulate the Design Example
8.4. Running the Hardware Tests x
8.4.1. Supported Boards 8.4.2. Steps to Compile the Design Example for Hardware 8.4.3. Steps to Run the Design Example on Hardware
8.4.2. Steps to Compile the Design Example for Hardware x
8.4.2.1. Steps to generate Routing Delay for PTP Enabled Designs
1. Introduction
2. Feature Description
3. Ethernet Subsystem Parameters
4. Subsystem IP Blocks
5. Interfaces and Signals
6. Recommended Clock Connections
7. Register Descriptions
8. Ethernet SS IP Example Design
9. Document Revision History for the Ethernet Subsystem Intel FPGA IP User Guide

4.3.1.2. get_hssi_profile for E-Tile

The SAL command get_hssi_profile is available only when dynamic reconfiguration is enabled. The table below shows the bit encoding for each dynamic reconfiguration group.
Table 15.   get_hssi_profile
Dynamic Reconfiguration Groups Current_Profile[6:4] or Next_Profile[6:4] Encoding
10/25G Ethernet+RS-FEC 3'b000
10/25G Ethernet Protocol+PTP+RS-FEC,CPRI 3'b001
CPRI Protocol 3'b010
100G Ethernet Protocol 3'b011

Each DR group can contain multiple profiles, and DR is only allowed for profiles within the same group. The table below shows the profiles listed under 10/25G Ethernet Protocol DR group and dynamic reconfiguration between these profiles is allowed. For example, you can choose to perform dynamic reconfiguration from existing "25G Ethernet + RS-FEC" to "10G Ethernet" profile and so on.

The default port profile upon power up is decided based on your selection in the subsystem GUI. If you select port 0 profile = "25G Ethernet + RS-FEC ", with dynamic reconfiguration enabled, and port 0 DR AIB mapping = port 0 (port 0 is reused after dynamic reconfiguration), when you enter the get_hssi_profile SAL command, NIOS can write the HSSI Read Data CSR with the value 7'b00000000.

Table 16.   get_hssi_profile
10/25GE Ethernet+RS-FEC
Dynamic Reconfiguration Groups Current_Profile[6:4] or Next_Profile[6:4] Encoding
Profile Current_Profile[3:0] or Next_Profile[3:0] Encoding
25G Ethernet + RSFEC 4'b0000
25G Ethernet 4'b0001
10G Ethernet 4'b0010

The following table shows the bit encoding for 25G Ethernet and CPRI profiles under 25G Ethernet + CPRI protocol DR group. The default port profile upon power up is determined by user selection in subsystem GUI. For example, if user selects port 0 profile = "25Gbe" and RS-FEC with PTP Enabled, with dynamic reconfiguration enabled, and port 0 DR AIB mapping = port 16 (port 0 packet stream will switch to port 16 after dynamic reconfiguration), when user issues get_hssi_profile SAL command, NIOS can write the HSSI Read Data CSR with the value 7'b0010000.

10/25G Ethernet Protocol+PTP+RSFEC, CPRI
Dynamic Reconfiguration Groups Current_Profile[6:4] or Next_Profile[6:4] Encoding
Profile Current_Profile[3:0] or Next_Profile[3:0] Encoding
25G Ethernet + 1588 PTP + RSFEC 4'b0000
25G Ethernet + 1588 PTP 4'b0001
10G Ethernet + 1588 PTP 4'b0010
24G CPRI + RSFEC 4'b0011
12G CPRI 4'b0100
10G CPRI 4'b0101
9.8G CPRI 4'b0110
4.9G CPRI 4'b0111
2.4G CPRI 4'b1000

The following table shows the bit encoding for CPRI profiles under CPRI protocol DR group. The default port profile upon power up is determined based on user selection in Ethernet subsystem GUI. For example, if user selects port 0 profile = "CPRI", with dynamic reconfiguration enabled, port 0 DR AIB mapping = port 0 (port 0 is reuse after dynamic reconfiguration), port 0 sub-profile 12G PCS, when user issues get_hssi_profile SAL command, NIOS can write the HSSI Read Data CSR with the value 7'b0100011.

Profile Current_Profile[3:0] or Next_Profile[3:0] Encoding
24G CPRI + RSFEC 4'b0000
24G CPRI 4'b0001
12G CPRI + RSFEC 4'b0010
12G CPRI 4'b0011
10G CPRI + RSFEC 4'b0100
10G CPRI 4'b0101
9.8G CPRI 4'b0110
4.9G CPRI 4'b0111
2.4G CPRI 4'b1000

The following table shows the bit encoding for 100/25G Ethernet profiles under 100G Ethernet protocol DR group. The default port profile upon power up is determined based on user selection in subsystem GUI. For example, if the user selects port 0 profile = "100GCAUI-4," with dynamic reconfiguration enabled, and port 0 DR AIB mapping = port 0 (after dynamic reconfiguration, the port 0 100G Ethernet packet stream will switch to port 0/1/2/3 25G Ethernet packet streams), when the user issues the get_hssi_profile SAL command, NIOS will write the HSSI Read Data CSR with the value 7'b0110000.

100G Ethernet Protocol
Profile Current_Profile[3:0] or Next_Profile[3:0] Encoding
1x100G MAC + PCS +RSFEC 4'b0000
1x100G MAC + PCS 4'b0001
4x25G MAC + PCS +RS-FEC 4'b0010
4x25G MAC + PCS 4'b0011
100G PAM4 with RS-FEC (544,514) (OSC ADP only) 4'b0100

100G NRZ with RS-FEC (544,514) (OSC ADP only)

 4'b0101
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