Ethernet Subsystem Intel® FPGA IP User Guide

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ID 773413
Date 4/03/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Feature Description 3. Ethernet Subsystem Parameters 4. Subsystem IP Blocks 5. Interfaces and Signals 6. Recommended Clock Connections 7. Register Descriptions 8. Ethernet SS IP Example Design 9. Document Revision History for the Ethernet Subsystem Intel FPGA IP User Guide
1. Introduction x
1.1. Supported Features 1.2. Device Family Support 1.3. Release Information 1.4. Resource Utilization 1.5. Getting Started
2. Feature Description x
2.1. Ethernet Subsystem Intel FPGA IP Overview 2.2. Supported Features
3. Ethernet Subsystem Parameters x
3.1. Parameter Editor Parameters 3.2. E-Tile Port Enablement Guidelines and Restrictions 3.3. F-Tile Ethernet Port to PMA Channel Mapping
4. Subsystem IP Blocks x
4.1. AXI Stream Bridge 4.2. CSR Address Decoder 4.3. Subsystem Abstraction Layer (SAL) 4.4. Dynamic Reconfiguration Extension Subsystem 4.5. IEEE 1588v2 PTP 4.6. Auto-Negotation and Link Training 4.7. Priority Flow Control
4.3. Subsystem Abstraction Layer (SAL) x
4.3.1. Subsystem Abstraction Layer (SAL) Commands
4.3.1. Subsystem Abstraction Layer (SAL) Commands x
4.3.1.1. NOP(0x0) 4.3.1.2. get_hssi_profile for E-Tile 4.3.1.3. get_hssi_profile for F-Tile 4.3.1.4. set_hssi_profile for E-Tile 4.3.1.5. set_hssi_profile for F-Tile 4.3.1.6. read_MAC_statistic 4.3.1.7. get_mtu 4.3.1.8. set_csr for E-Tile 4.3.1.9. set_csr for F-Tile 4.3.1.10. get_csr for E-Tile 4.3.1.11. get_csr for F-Tile 4.3.1.12. enable_loopback for E-Tile 4.3.1.13. enable_loopback for F-Tile 4.3.1.14. disable_loopback for E-Tile 4.3.1.15. disable_loopback for F-Tile 4.3.1.16. Reset MAC Statistics 4.3.1.17. set_mtu for F-Tile 4.3.1.18. Ncsi_get_link_status 4.3.1.19. Reserved 4.3.1.20. firmware_version (0xFF)
4.5. IEEE 1588v2 PTP x
4.5.1. TX PTP Classifier
5. Interfaces and Signals x
5.1. AXI4 Interfaces 5.2. Serial Interface 5.3. Clocks 5.4. Resets
5.1. AXI4 Interfaces x
5.1.1. AXI-Lite CSR 5.1.2. AXI-ST Client Interface 5.1.3. AXI-ST PHY Direct 5.1.4. AXI-ST PTP 5.1.5. Flow Control
6. Recommended Clock Connections x
6.1. Driving Multiple Ports with the Same Clock 6.2. Clock Connections for MAC Async Client FIFO 6.3. F-Tile Clock Connections for PTP Synchronous and Asynchronous cases 6.4. Clock Connections for SyncE Operation on E-Tile 6.5. Clock Connections for SyncE Operation on F-Tile 6.6. F-Tile PMA and FEC Direct PHY IP Clock Output
7. Register Descriptions x
7.1. Subsystem Registers 7.2. Port Registers 7.3. F-Tile Address Maps 7.4. F-Tile ANLT Port Register Map 7.5. F-Tile PTP Tile Adapter Register Map 7.6. F-Tile DR Controller Register Map
7.1. Subsystem Registers x
7.1.1. Device Feature Header Lo 7.1.2. Device Feature Header Hi 7.1.3. Feature GUID_L 7.1.4. Feature GUID_H 7.1.5. Feature CSR ADDR 7.1.6. Feature CSR Size Group 7.1.7. Version 7.1.8. Feature List 7.1.9. Interface Attribute Port X Parameters 7.1.10. HSSI Command/Status 7.1.11. HSSI Control/Address 7.1.12. HSSI Read Data 7.1.13. HSSI Write Data 7.1.14. HSSI Ethernet Port X Status 7.1.15. Priority Flow Control 7.1.16. Priority Flow Control TX Queue Statistics 7.1.17. Priority Flow Control RX Queue Statistics 7.1.18. Priority Flow Control TX Queue Threshold 7.1.19. Priority Flow Control RX Queue Threshold 7.1.20. F-Tile DR Controller Status
7.2. Port Registers x
7.2.1. PTP Packet Classifier Registers
7.2.1. PTP Packet Classifier Registers x
7.2.1.1. Recognized and Unrecognized Packet Counters 7.2.1.2. Parse Graph Specific Packet Counters
8. Ethernet SS IP Example Design x
8.1. Steps to Generate the Example Design 8.2. Supported Simulators 8.3. Running the Simulation Tests 8.4. Running the Hardware Tests
8.3. Running the Simulation Tests x
8.3.1. Steps to Simulate the Design Example
8.4. Running the Hardware Tests x
8.4.1. Supported Boards 8.4.2. Steps to Compile the Design Example for Hardware 8.4.3. Steps to Run the Design Example on Hardware
8.4.2. Steps to Compile the Design Example for Hardware x
8.4.2.1. Steps to generate Routing Delay for PTP Enabled Designs
1. Introduction
2. Feature Description
3. Ethernet Subsystem Parameters
4. Subsystem IP Blocks
5. Interfaces and Signals
6. Recommended Clock Connections
7. Register Descriptions
8. Ethernet SS IP Example Design
9. Document Revision History for the Ethernet Subsystem Intel FPGA IP User Guide

7.1.14. HSSI Ethernet Port X Status

Description: HSSI Ethernet Port X Status X = 0 to 15 (E-Tile) and 0 to 19 (F-Tile) Depends on NUM_ENABLED_PORTS parameter, read returns reserved value 0 if port does not exist.

Port 0-15 Byte Offset: 0xC0 + X (0x00 - 0x0F) *4

Port 16-19 Byte Offset: 0x200 + X (0x00 - 0x0F) * 4

Addressing Mode: 32 bits

Bit Type Reset Description
31:27 RO 0 Reserved
26:26 W1C 0 Parity Error on received packet
25:24 RO 0

PTP channels Tx_pll_locked (o_ehip{0..NUM_PORT/2}_tx_pll_locked, applicable only in E-tile.

Port X = 0 - 3,

[25:25] o_ehip1_tx_pll_locked

[24:24] o_ehip0_tx_pll_locked

Port X = 4 - 7,

[25:25] o_ehip3_tx_pll_locked

[24:24] o_ehip2_tx_pll_locked

Port X = 8 - 11,

[25:25] o_ehip5_tx_pll_locked

[24:24] o_ehip4_tx_pll_locked

Port X = 12 - 15,

[25:25] o_ehip7_tx_pll_locked

[24:24] o_ehip6_tx_pll_locked
23:23 RO 0

Tx_pll_locked

Tx Ethernet port pll lock
22:22 RO 0

Rx_pcs_ready:

Asserted when the RX lanes of the corresponding Ethernet port are fully aligned and ready to receive data.

21:21 RO 0

Tx_lanes_stable:

Asserted when physical TX lanes are stable and ready to transmit data for the corresponding Ethernet port.

20:20 RO 0

Ical/pcal error:

Indicate ical/pcal operation timeout after 20s of status polling on PMA AVMM register 0x207.

Applicable only for E-tile
19:19 RO 0

load_recipe_error:

Indicate the load recipe timeout when reading PMA Configuration Loading Status CSR (0x40144 bit 1 set to 1). Another condition to set this error bit is when timeout after 20s, i.e load finish (0x40144 bit 0) not asserted or load timeout (0x40144 bit 1) asserted after 20sec.

Applicable only for E-tile
18:18 RO 0

eth_mode:

Ethernet mode. This signal is set to 1 when the MAC function is configured to operate at 1000 Mbps; set to 0 when it is configured to operate at 10/100 Mbps.

Only applicable for TSE_MAC profile. Reserved for other profiles.
17:17 RO 0

ena_10:

10 Mbps enable. This signal is set to 1 to indicate that the PHY interface should operate at 10 Mbps. Valid only when the eth_mode signal is set to 0.

Only applicable for TSE_MAC profile. Reserved for other profiles.
16:16 RO 0

set_1000:

Gigabit mode selection. Can be driven to 1 by an external device, for example a PHY device, to set the MAC function to operate in gigabit. When set to 0, the MAC is set to operate in 10/100 Mbps. This signal is ignored when the ETH_SPEED bit in the command_config register is set to 1.

Only applicable for TSE_MAC profile. Reserved for other profiles.
15:15 RO 0

set_10:

10 Mbps selection. Can be driven to 1 by an external device, for example a PHY device, to indicate that the MAC function is connected to a 10-Mbps PHY device.

When set to 0, the MAC function is set to operate in 100-Mbps or gigabit mode.

This signal is ignored when the ETH_SPEED or ENA_10 bit in the command_config register is set to 1. The ENA_10 bit has a higher priority than this signal.

Only applicable for TSE_MAC profile. Reserved for other profiles.
14:13 RO 0

mac_eccstatus[1:0]:

Indicates the ECC status. This signal is synchronized to the reg_clk clock domain.

  • 11: An uncorrectable error occurred and the error data appears at the output.
  • 10: A correctable error occurred and the error has been corrected at the output. However, the memory array has not been updated.
  • 01: Not valid.
  • 00: No error.

Only applicable for TSE_MAC profile. Reserved for other profiles.
12:11 RO 0

pcs_eccstatus[1:0]:

Indicates the ECC status. This signal is synchronized to the reg_clk clock domain.

  • 11: An uncorrectable error occurred and the error data appears at the output.
  • 10: A correctable error occurred and the error has been corrected at the output.
  • 01: Not valid.
  • 00: No error.

Only applicable for TSE_PCS profile. Reserved for other profiles.
10:10 RO 0

unidirectional_remote_fault_dis:

When asserted, this signal indicates the state of the tx_unidir_control register bit 1.

Not applicable for E-tile.
9:9 RO 0

unidirectional_force_remote_fault:

When asserted, this signal indicates the state of the tx_unidir_control register bit 2.

Not applicable for E-tile.
8:8 W1C 0

remote_fault_status:

Asserted when the RX MAC of the corresponding Ethernet channel detects a remote fault: the remote link partner sent remote fault ordered sets indicating that it is unable to receive data. This signal is functional only if you set the Choose Link Fault generation option parameter to the value of Bidirectional in the parameter editor or if you overwrite the parameter editor parameter by setting the link_fault_mode RTL parameter to the value of lf_bidir.

7:7 W1C 0

local_fault_status:

Asserted when the RX MAC of the corresponding Ethernet channel

detects a local fault: the RX PCS detected a problem that prevents it from receiving data. This signal is functional only if you set the Choose Link Fault generation option parameter to the value of Bidirectional or Unidirectional in the parameter editor or if you overwrite the parameter editor parameter by setting the link_fault_mode RTL parameter to the value of lf_bidir or lf_unidir.

6:6 RO 0

unidirectional_en:

Asserted if the IP core includes Clause 66 for unidirectional support. This signal is available if you turn on Enable link fault generation in the parameter editor.

Not applicable for E-tile.
5:5 RO 0

link_fault_gen_en:

Asserted if the IP core includes Clause 66 for unidirectional support. This signal is available if you turn on Enable link fault generation in the parameter editor.

Not applicable for E-tile.
4:4 RO 0

rx_block_lock:

Asserted when the corresponding Ethernet channel completes 66-bit block boundary alignment on all PCS lanes. Each channel has its own block lock signal.

3:3 RO 0

rx_am_lock:

Asserted when the RX PCS completes detection of alignment markers and deskew of the virtual PCS lanes in the corresponding Ethernet 100G channel.

2:2 RO 0

o_cdr_lock:

Indicates that the recovered clocks are locked to data. The o_clk_rec_div64[n] and o_clk_rec_div66[n] clocks are reliable only after o_cdr_lock[n] is asserted.

1:1 RO 0

o_rx_hi_ber:

Asserted to indicate the RX PCS of the corresponding Ethernet channel is in a HI BER state according to Figure 82-15 in the IEEE 802.3-2015 Standard. The IP core uses this signal in auto negotiation and link training.

0:0 RO 0

o_ehip_ready:

The Ethernet channel deasserts this signal in response to an i_csr_rst_n or i_tx_rst_n reset, or either of the corresponding soft resets. After the reset process completes, the channel reasserts this signal to indicate that the Hard IP for Ethernet block has completed initialization and is ready to interoperate with the main Stratix® 10 die. While the o_ehip_ready signal is low, the channel's datapath is not ready for data on the client interface nor ready for register accesses on the Ethernet reconfiguration interface.

Applicable for E-tile.
Level Two Title