Ethernet Subsystem Intel® FPGA IP User Guide

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ID 773413
Date 4/03/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Feature Description 3. Ethernet Subsystem Parameters 4. Subsystem IP Blocks 5. Interfaces and Signals 6. Recommended Clock Connections 7. Register Descriptions 8. Ethernet SS IP Example Design 9. Document Revision History for the Ethernet Subsystem Intel FPGA IP User Guide
1. Introduction x
1.1. Supported Features 1.2. Device Family Support 1.3. Release Information 1.4. Resource Utilization 1.5. Getting Started
2. Feature Description x
2.1. Ethernet Subsystem Intel FPGA IP Overview 2.2. Supported Features
3. Ethernet Subsystem Parameters x
3.1. Parameter Editor Parameters 3.2. E-Tile Port Enablement Guidelines and Restrictions 3.3. F-Tile Ethernet Port to PMA Channel Mapping
4. Subsystem IP Blocks x
4.1. AXI Stream Bridge 4.2. CSR Address Decoder 4.3. Subsystem Abstraction Layer (SAL) 4.4. Dynamic Reconfiguration Extension Subsystem 4.5. IEEE 1588v2 PTP 4.6. Auto-Negotation and Link Training 4.7. Priority Flow Control
4.3. Subsystem Abstraction Layer (SAL) x
4.3.1. Subsystem Abstraction Layer (SAL) Commands
4.3.1. Subsystem Abstraction Layer (SAL) Commands x
4.3.1.1. NOP(0x0) 4.3.1.2. get_hssi_profile for E-Tile 4.3.1.3. get_hssi_profile for F-Tile 4.3.1.4. set_hssi_profile for E-Tile 4.3.1.5. set_hssi_profile for F-Tile 4.3.1.6. read_MAC_statistic 4.3.1.7. get_mtu 4.3.1.8. set_csr for E-Tile 4.3.1.9. set_csr for F-Tile 4.3.1.10. get_csr for E-Tile 4.3.1.11. get_csr for F-Tile 4.3.1.12. enable_loopback for E-Tile 4.3.1.13. enable_loopback for F-Tile 4.3.1.14. disable_loopback for E-Tile 4.3.1.15. disable_loopback for F-Tile 4.3.1.16. Reset MAC Statistics 4.3.1.17. set_mtu for F-Tile 4.3.1.18. Ncsi_get_link_status 4.3.1.19. Reserved 4.3.1.20. firmware_version (0xFF)
4.5. IEEE 1588v2 PTP x
4.5.1. TX PTP Classifier
5. Interfaces and Signals x
5.1. AXI4 Interfaces 5.2. Serial Interface 5.3. Clocks 5.4. Resets
5.1. AXI4 Interfaces x
5.1.1. AXI-Lite CSR 5.1.2. AXI-ST Client Interface 5.1.3. AXI-ST PHY Direct 5.1.4. AXI-ST PTP 5.1.5. Flow Control
6. Recommended Clock Connections x
6.1. Driving Multiple Ports with the Same Clock 6.2. Clock Connections for MAC Async Client FIFO 6.3. F-Tile Clock Connections for PTP Synchronous and Asynchronous cases 6.4. Clock Connections for SyncE Operation on E-Tile 6.5. Clock Connections for SyncE Operation on F-Tile 6.6. F-Tile PMA and FEC Direct PHY IP Clock Output
7. Register Descriptions x
7.1. Subsystem Registers 7.2. Port Registers 7.3. F-Tile Address Maps 7.4. F-Tile ANLT Port Register Map 7.5. F-Tile PTP Tile Adapter Register Map 7.6. F-Tile DR Controller Register Map
7.1. Subsystem Registers x
7.1.1. Device Feature Header Lo 7.1.2. Device Feature Header Hi 7.1.3. Feature GUID_L 7.1.4. Feature GUID_H 7.1.5. Feature CSR ADDR 7.1.6. Feature CSR Size Group 7.1.7. Version 7.1.8. Feature List 7.1.9. Interface Attribute Port X Parameters 7.1.10. HSSI Command/Status 7.1.11. HSSI Control/Address 7.1.12. HSSI Read Data 7.1.13. HSSI Write Data 7.1.14. HSSI Ethernet Port X Status 7.1.15. Priority Flow Control 7.1.16. Priority Flow Control TX Queue Statistics 7.1.17. Priority Flow Control RX Queue Statistics 7.1.18. Priority Flow Control TX Queue Threshold 7.1.19. Priority Flow Control RX Queue Threshold 7.1.20. F-Tile DR Controller Status
7.2. Port Registers x
7.2.1. PTP Packet Classifier Registers
7.2.1. PTP Packet Classifier Registers x
7.2.1.1. Recognized and Unrecognized Packet Counters 7.2.1.2. Parse Graph Specific Packet Counters
8. Ethernet SS IP Example Design x
8.1. Steps to Generate the Example Design 8.2. Supported Simulators 8.3. Running the Simulation Tests 8.4. Running the Hardware Tests
8.3. Running the Simulation Tests x
8.3.1. Steps to Simulate the Design Example
8.4. Running the Hardware Tests x
8.4.1. Supported Boards 8.4.2. Steps to Compile the Design Example for Hardware 8.4.3. Steps to Run the Design Example on Hardware
8.4.2. Steps to Compile the Design Example for Hardware x
8.4.2.1. Steps to generate Routing Delay for PTP Enabled Designs
1. Introduction
2. Feature Description
3. Ethernet Subsystem Parameters
4. Subsystem IP Blocks
5. Interfaces and Signals
6. Recommended Clock Connections
7. Register Descriptions
8. Ethernet SS IP Example Design
9. Document Revision History for the Ethernet Subsystem Intel FPGA IP User Guide

4.3.1.5. set_hssi_profile for F-Tile

This SAL command is used to program the profile information to the DR CSR registers and set the Trigger Reconfig bit to start the DR sequence. The DR completion status is reflected in HSSI Command/Status CSR bit [3:2] with error indication shown in bit 4. This set_hssi_profile SAL command is executed in HW and not through SAL NIOS firmware to avoid extra latency introduced in the DR sequence.
Table 22.   set_hssi_profile
SAL command Write CSR Read CSR (polling) CSR Values
set_hssi_profile

HSSI Command/Status [0:0] = 0 (read command)

HSSI Command/Status [1:1] = 1 (write command)

HSSI Command/Status [2:2] = 0 (reset ACK_TRANS)

HSSI Command/Status [3:3] = 0 (not busy)

HSSI Command/Status [0:0] = 0 (read command)

HSSI Command/Status [1:1] = 1 (write command)

HSSI Command/Status [2:2] = 1 (transfer completed)

HSSI Command/Status [3:3] = 0 (not busy)

 dyn_rcfg_dr_trigger_reg [0:0] - Trigger Reconfig
set_hssi_profile dyn_rcfg_dr_next_profile_0_reg [18:18] - Disable CPI command = 1 (simulation), 0 (silicon)
[17:17] - Start up IP restore indicator = 0
[16:16] - Final State Neutral Profile Indicator = 1
HSSI Write Data[19:15] = 0 [15:15] - Next Profile 0 Indicator = 0 (active profile)
HSSI Write Data[14:0] - Next Profile 0 N/A [14:0] - Next Profile 0
set_hssi_profile HSSI Write Data[19:15] = 2 dyn_rcfg_dr_next_profile_1_reg [31:31] - Next Profile 2 Indicator = 0 (active profile)
HSSI Write Data[14:0] - Next Profile 2 [30:16] - Next Profile 2
set_hssi_profile HSSI Write Data[19:15] = 1 [15:15] - Next Profile 1 Indicator = 0 (active profile)
HSSI Write Data[14:0] - Next Profile 1 [14:0] - Next Profile 1
set_hssi_profile HSSI Write Data[19:15] = 4 dyn_rcfg_dr_next_profile_2_reg [31:31] - Next Profile 4 Indicator = 0 (active profile)
HSSI Write Data[14:0] - Next Profile 4 [30:16] - Next Profile 4
set_hssi_profile HSSI Write Data[19:15] = 3 [15:15] - Next Profile 3 Indicator = 0 (active profile)
HSSI Write Data[14:0] - Next Profile 3 [14:0] - Next Profile 3
: : : : :
set_hssi_profile HSSI Write Data[19:15] = 1D Profile Selection Register (0x200)

profile_sel[5:0]

profile_sel[1:0] indicates sum of bandwidth (BW) of all active ports in selected profile
  • 2’b00 – Max BW in Reconfig Group
  • 2’b01 – Max BW / 2 in Reconfig Group
  • 2’b10 – Max BW / 4 in Reconfig Group
  • 2’b11 – Special rate (like 40GE)
profile_sel[3:2] indicates number of XCVR lanes which are active in selected profile
  • 2’b00 – Max no of lanes in Reconfig Group
  • 2’b01 – Max no of lanes / 2 in Reconfig Group
  • 2’b10 – Max no of lanes / 4 in Reconfig Group
profile_sel[5:4] indicates number of active ports in selected profile
  • 2’b00 – 1 port
  • 2’b01 – 2 ports
  • 2’b10 – 4 ports

FGT:

25GE-1 Reconfigurable

6’b00_00_00 - “1x25GE-1/10GE-1”

(use 0x208 for 10GE/25GE selection)

50GE-1 Reconfigurable

6’b00_00_00 - “1x50GE-1”

6’b00_00_01 - “1x25GE-1/10GE-1”

(use 0x208 for 10GE/25GE selection)

100GE-4 Reconfigurable

6’b00_00_00 - “1x100GE-4”

6’b00_00_11 - “1x40GE-4”

6’b00_01_00 - “1x100GE-2”

6’b01_00_00 - “2x50GE-2”

6’b01_01_00 - “2x50GE-1”

6’h10_00_00 - “4x25GE-1/10GE-1”

(use 0x208 for 10GE/25GE selection)

100GE-2 Reconfigurable

6’b00_00_00 - “1x100GE-2”

6’b00_00_01 - “1x50GE-2”

6’b01_00_00 - “2x50GE-1”

6’b01_00_01 - “2x25GE-1/10GE-1”

(use 0x208 for 10GE/25GE selection)

400GE-8 Reconfigurable

6’b00_00_00 - “1x400GE-8”

6’b01_00_00 - “2x200GE-4”

6’b10_00_00 - “4x100GE-2”

200GE-4 Reconfigurable

6’b00_00_00 - “1x200GE-4”

6’b00_00_01 - “1x100GE-4”

6’b01_00_00 - “2x100GE-2”

6’b01_00_01 - “2x50GE-2”

6’b10_00_00 - “4x50GE-1”

FHT:

50GE-1 Reconfigurable

6’b00_00_00 – “1x50GE-1”

6’b00_00_01 - “1x25GE-1”

100GE-4 Reconfigurable

6’b00_00_00 - “1x100GE-4”

6’b00_01_00 - “1x100GE-2”

6’b00_10_00 – “1x100GE-1”

6’b01_00_00 - “2x50GE-2”

6’b01_01_00 - “2x50GE-1”

6’h10_00_00 - “4x25GE-1”

100GE-2 Reconfigurable

6’b00_00_00 - “1x100GE-2”

6’b00_01_00 – “1x100GE-1”

6’b00_00_01 - “1x50GE-2”

6’b01_00_00 - “2x50GE-1”

6’b01_00_01 - “2x25GE-1”

100GE-1 Reconfigurable

6’b00_00_00 – “1x100GE-1”

6’b00_00_01 - “1x50GE-1”

6’b00_00_10 - “1x25GE-1”

400GE-4 Reconfigurable

6’b00_00_00 - “1x400GE-4”

6’b00_00_01 - “1x200GE-4”

6’b01_00_00 - “2x200GE-2”

6’b01_00_01 - “2x100GE-2”

6’b10_00_00 - “4x100GE-1”

200GE-4 Reconfigurable

6’b00_00_00 - “1x200GE-4”

6’b00_01_00 - “1x200GE-2”

6’b00_00_01 - “1x100GE-4”

6’b01_00_00 - “2x100GE-2”

6’b01_01_00 – “2x100GE-1”

6’b01_00_01 - “2x50GE-2”

6’b10_00_00 - “4x50GE-1”

200GE-2 Reconfigurable

6’b00_00_00 - “1x200GE-2”

6’b00_00_01 - “1x100GE-2”

6’b00_00_10 - “1x50GE-2”

6’b01_00_00 - “2x100GE-1”

6’b01_00_01 - “2x50GE-1”
set_hssi_profile HSSI Write Data[19:15] = 1E 10GE/25GE Selection Register

sel_25g_10g [3:0]

User to set these bits to select 10GE or 25GE for the active ports in the selected profile. Bit definition as below.

1’b0 – 25GE is selected

1’b1 – 10GE is selected

Bit 0 – Select 25GE/10GE for Port 0

Bit 1 – Select 25GE/10GE for Port 1

Bit 2 – Select 25GE/10GE for Port 2

Bit 3 – Select 25GE/10GE for Port 3

Note that the port specific bits only apply to the active ports in the selected profile.

This register is applicable only to the following profiles in FGT Reconfig Groups:
  • 4x 25GE/10GE profile in 100GE-4 Group
  • 2x 25GE/10GE profile in 100GE-2 Group
  • 1x 25GE/10GE profile in 25GE-1 & 50GE-1 Group

This register is not applicable for any FHT Reconfig Groups as 10GE rate is not supported by FHT
set_hssi_profile HSSI Write Data[19:15] = 1F - dyn_rcfg_dr_avmm_timeout_reg HSSI Write Data[31:0]
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