Ethernet Subsystem Intel® FPGA IP User Guide

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ID 773413
Date 4/03/2023
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Feature Description 3. Ethernet Subsystem Parameters 4. Subsystem IP Blocks 5. Interfaces and Signals 6. Recommended Clock Connections 7. Register Descriptions 8. Ethernet SS IP Example Design 9. Document Revision History for the Ethernet Subsystem Intel FPGA IP User Guide
1. Introduction x
1.1. Supported Features 1.2. Device Family Support 1.3. Release Information 1.4. Resource Utilization 1.5. Getting Started
2. Feature Description x
2.1. Ethernet Subsystem Intel FPGA IP Overview 2.2. Supported Features
3. Ethernet Subsystem Parameters x
3.1. Parameter Editor Parameters 3.2. E-Tile Port Enablement Guidelines and Restrictions 3.3. F-Tile Ethernet Port to PMA Channel Mapping
4. Subsystem IP Blocks x
4.1. AXI Stream Bridge 4.2. CSR Address Decoder 4.3. Subsystem Abstraction Layer (SAL) 4.4. Dynamic Reconfiguration Extension Subsystem 4.5. IEEE 1588v2 PTP 4.6. Auto-Negotation and Link Training 4.7. Priority Flow Control
4.3. Subsystem Abstraction Layer (SAL) x
4.3.1. Subsystem Abstraction Layer (SAL) Commands
4.3.1. Subsystem Abstraction Layer (SAL) Commands x
4.3.1.1. NOP(0x0) 4.3.1.2. get_hssi_profile for E-Tile 4.3.1.3. get_hssi_profile for F-Tile 4.3.1.4. set_hssi_profile for E-Tile 4.3.1.5. set_hssi_profile for F-Tile 4.3.1.6. read_MAC_statistic 4.3.1.7. get_mtu 4.3.1.8. set_csr for E-Tile 4.3.1.9. set_csr for F-Tile 4.3.1.10. get_csr for E-Tile 4.3.1.11. get_csr for F-Tile 4.3.1.12. enable_loopback for E-Tile 4.3.1.13. enable_loopback for F-Tile 4.3.1.14. disable_loopback for E-Tile 4.3.1.15. disable_loopback for F-Tile 4.3.1.16. Reset MAC Statistics 4.3.1.17. set_mtu for F-Tile 4.3.1.18. Ncsi_get_link_status 4.3.1.19. Reserved 4.3.1.20. firmware_version (0xFF)
4.5. IEEE 1588v2 PTP x
4.5.1. TX PTP Classifier
5. Interfaces and Signals x
5.1. AXI4 Interfaces 5.2. Serial Interface 5.3. Clocks 5.4. Resets
5.1. AXI4 Interfaces x
5.1.1. AXI-Lite CSR 5.1.2. AXI-ST Client Interface 5.1.3. AXI-ST PHY Direct 5.1.4. AXI-ST PTP 5.1.5. Flow Control
6. Recommended Clock Connections x
6.1. Driving Multiple Ports with the Same Clock 6.2. Clock Connections for MAC Async Client FIFO 6.3. F-Tile Clock Connections for PTP Synchronous and Asynchronous cases 6.4. Clock Connections for SyncE Operation on E-Tile 6.5. Clock Connections for SyncE Operation on F-Tile 6.6. F-Tile PMA and FEC Direct PHY IP Clock Output
7. Register Descriptions x
7.1. Subsystem Registers 7.2. Port Registers 7.3. F-Tile Address Maps 7.4. F-Tile ANLT Port Register Map 7.5. F-Tile PTP Tile Adapter Register Map 7.6. F-Tile DR Controller Register Map
7.1. Subsystem Registers x
7.1.1. Device Feature Header Lo 7.1.2. Device Feature Header Hi 7.1.3. Feature GUID_L 7.1.4. Feature GUID_H 7.1.5. Feature CSR ADDR 7.1.6. Feature CSR Size Group 7.1.7. Version 7.1.8. Feature List 7.1.9. Interface Attribute Port X Parameters 7.1.10. HSSI Command/Status 7.1.11. HSSI Control/Address 7.1.12. HSSI Read Data 7.1.13. HSSI Write Data 7.1.14. HSSI Ethernet Port X Status 7.1.15. Priority Flow Control 7.1.16. Priority Flow Control TX Queue Statistics 7.1.17. Priority Flow Control RX Queue Statistics 7.1.18. Priority Flow Control TX Queue Threshold 7.1.19. Priority Flow Control RX Queue Threshold 7.1.20. F-Tile DR Controller Status
7.2. Port Registers x
7.2.1. PTP Packet Classifier Registers
7.2.1. PTP Packet Classifier Registers x
7.2.1.1. Recognized and Unrecognized Packet Counters 7.2.1.2. Parse Graph Specific Packet Counters
8. Ethernet SS IP Example Design x
8.1. Steps to Generate the Example Design 8.2. Supported Simulators 8.3. Running the Simulation Tests 8.4. Running the Hardware Tests
8.3. Running the Simulation Tests x
8.3.1. Steps to Simulate the Design Example
8.4. Running the Hardware Tests x
8.4.1. Supported Boards 8.4.2. Steps to Compile the Design Example for Hardware 8.4.3. Steps to Run the Design Example on Hardware
8.4.2. Steps to Compile the Design Example for Hardware x
8.4.2.1. Steps to generate Routing Delay for PTP Enabled Designs
1. Introduction
2. Feature Description
3. Ethernet Subsystem Parameters
4. Subsystem IP Blocks
5. Interfaces and Signals
6. Recommended Clock Connections
7. Register Descriptions
8. Ethernet SS IP Example Design
9. Document Revision History for the Ethernet Subsystem Intel FPGA IP User Guide

4.3.1.4. set_hssi_profile for E-Tile

The bit encoding of each profile within DR groups are shown in section Get_hssi_profile . When profile switching is finished, NIOS writes 1 to the BUSY bit in the HSSI Command/Status CSR to indicate that the DR operation is in process. Once the DR operation is completed, NIOS sets the ACK_TRANS and ERROR bits to indicate success or failure of the operation.

The following limitations are enforced on valid profile switching when the user performs dynamic reconfiguration:
  1. Cross-DR group profile swapping is not permitted.
    • For example, profiles inside the 100G Ethernet protocol are not permitted.
    • Profiles within 25G Ethernet + CPRI, 10/25G Ethernet DR groups, and so on are not permitted.
  2. Valid profile switching within the DR group is shown below.
    Table 18.  10/25G Ethernet Protocol
    With PTP Enabled Without PTP Enabled
    25G_PTP_FEC ->25G_PTP_noFEC 25G_FEC -> 25G
    25G_PTP_noFEC ->25G_PTP_FEC 25G_FEC ->10G
    25G_PTP_FEC ->10G_PTP 25G -> 25G_FEC
    10G_PTP-> 25G_PTP_FEC 25G -> 10G
    25G_PTP_noFEC -> 10G_PTP 10G -> 25G
    10G_PTP -> 25G_PTP_noFEC 10G -> 25G_FEC
    Table 19.  CPRI
    100G Ethernet
    25G_PTP_FEC ->24G_CPRI + FEC
    25G_PTP_FEC ->12G_CPRI
    25G_PTP_FEC ->10G_CPRI
    25G_PTP_FEC->9.8G CPRI
    25G_PTP_FEC ->4.9G CPRI
    25G_PTP_FEC ->2.4G CPRI
    24G_CPRI +_FEC ->12G CPRI
    24G_CPRI +_FEC ->10G CPRI
    12G CPRI ->10G CPRI
    10G CPRI ->9.8G CPRI
    9.8G CPRI ->4.9G CPRI
    4.9G CPRI ->2.4G CPRI
    2.4G CPRI->24G CPRI + FEC
    The CPRI protocol can switch between any line rate.
    Table 20.  10/25G Ethernet + CPRI Protocol
    10/25G Ethernet + CPRI protocol
    25G_PTP_RS-FEC -> CPRI_24G_RS-FEC
    CPRI_24G_RS-FEC -> 25G_PTP_RS-FEC
    25G_PTP_RS-FEC -> CPRI_10G
    CPRI_10G -> 25G_PTP_RS-FEC
    25G_PTP_RS-FEC -> CPRI_9p8G
    CPRI_9p8G -> 25G_PTP_RS-FEC
    25G_PTP_RS-FEC -> CPRI_4p9G
    CPRI_4p9G -> 25G_PTP_RS-FEC
    25G_PTP_RS-FEC -> CPRI_2p4G
    CPRI_2p4G -> 25G_PTP_RS-FEC
    CPRI_24G_RS-FEC -> CPRI_12G
    CPRI_12G -> CPRI_10G
    CPRI_10G -> CPRI_9p8G
    CPRI_9p8G -> CPRI_4p9G
    CPRI_4p9G -> CPRI_2p4G
    CPRI_2p4G -> CPRI_24G_RS-FEC
    25G_PTP_RS-FEC -> 10G_PTP
    10G_PTP -> 25G_PTP_RS-FEC
    25G_PTP_RS-FEC -> CPRI_12G
    CPRI_12G -> 25G_PTP_RS-FEC
    Table 21.  100G Ethernet
    100G Ethernet
    100G MAC + PCS -> 4x25G MAC + PCS
    100G MAC + PCS + RS-FEC -> 4x25G MAC + PCS + RS-FEC
    100G NRZ with RSFEC (528,514) / without RSFEC <-> 100G NRZ with RS-FEC (544,514) (Applicable only in Intel® IPU Platform F2000X-PL)
    100G NRZ with RSFEC (528,514) / without RSFEC <-> 100G PAM4 RSFEC (544,514) (Applicable only in Intel® IPU Platform F2000X-PL)
    Note:
    • The current release does not support external AIB clocking or PTP.
    • There is no direct DR transition support between 100G PAM4 and 4x25G NRZ modes.
  3. Initiating DR through direct CSR writes is not supported. You should always use the SAL to trigger the DR flow.

    If the DR flow triggered by SAL fails due to a timeout (SAL error bit set), you should reset the transceiver channel by writing to PHY_CONFIG (0x310 offset) register bit 0-2 (Soft CSR/TX/RX reset) for that specific transceiver CSR register space.

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