Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

5.2. FPGA Manager Block Diagram and System Integration

Figure 15. FPGA Manager Block Diagram

The register slave interface connects to the level 4 (L4) master peripheral bus for control and status register (CSR) access. The configuration slave interface connects to the level 3 (L3) interconnect for the microprocessor unit (MPU) subsystem or other masters to write the FPGA configuration image to the FPGA control block (CB) when configuring the FPGA portion of the SoC device.

The general-purpose I/O and boot handshake input interfaces connect to the FPGA fabric. The FPGA manager also connects to the FPGA CB signals to monitor and control the FPGA portion of the device.

The FPGA manager consists of the following blocks:

  • Configuration slave interface—accepts and transfers the configuration image to the data interface.
  • Register slave interface—accesses the CSRs in the FPGA manager.
  • Data—accepts the FPGA configuration image from the configuration slave interface and sends it to the FPGA CB.
  • Control—controls the FPGA CB.
  • Monitor—monitors the configuration signals in the FPGA CB and sends interrupts to the MPU subsystem.
  • Fabric I/O—reads and writes signals from or to the FPGA fabric.