Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

28.1.4. Interrupts

Table 220.   FPGA-to-HPS Interrupts Interface
Parameter Name Parameter Description Interface Name
Enable FPGA-to-HPS Interrupts Enables the interface for FPGA interrupt signals to the MPU (in the HPS).

f2h_irq0

f2h_irq1

You can enable the interfaces for each HPS peripheral interrupt to the FPGA.

Table 221.  HPS-to-FPGA Interrupts InterfaceThe following table lists the available HPS-to-FPGA interrupt interfaces and the corresponding parameters to enable them.
Parameter Name Parameter Description Interface Name
Enable CAN interrupts Enables the interface for HPS CAN controllers interrupt to the FPGA

h2f_can0_interrupt

h2f_can1_interrupt

Enable clock peripheral interrupts Enables the interface for HPS clock manager and MPU wake-up interrupt signals to the FPGA

h2f_clkmgr_interrupt

h2f_mpuwakeup_interrupt

Enable CTI interrupts Enables the interface for HPS cross-trigger interrupt signals to the FPGA

h2f_cti_interrupt0

h2f_cti_interrupt1

Enable DMA interrupts Enables the interface for HPS DMA channels interrupt and DMA abort interrupt to the FPGA

h2f_dma_interrupt0

h2f_dma_interrupt1

h2f_dma_interrupt2

h2f_dma_interrupt3

h2f_dma_interrupt4

h2f_dma_interrupt5

h2f_dma_interrupt6

h2f_dma_interrupt7

h2f_dma_abort_interrupt

Enable EMAC interrupts Enables the interface for HPS Ethernet MAC controller interrupt to the FPGA

h2f_emac0_interrupt

h2f_emac1_interrupt

Enable FPGA manager interrupts Enables the interface for the HPS FPGA manager interrupt to the FPGA

h2f_fpga_man_interrupt

Enable GPIO interrupts Enables the interface for the HPS general purpose IO (GPIO) interrupt to the FPGA

h2f_gpio0_interrupt

h2f_gpio1_interrupt

h2f_gpio2_interrupt

Enable I2C-EMAC interrupts (for I2C2 and I2C3) Enables the interface for the HPS I2C interrupt to the FPGA (I2C used for EMAC media interface control)

h2f_i2c_emac0_interrupt

h2f_i2c_emac1_interrupt

Enable I2C peripheral interrupts (for I2C0 and I2C1) Enables the interface for the HPS I2C interrupt to the FPGA (I2C used for general purpose)

h2f_i2c0 _interrupt

h2f_i2c1_interrupt

Enable L4 timer interrupts Enables the interface for the HPS SP timer interrupt to the FPGA. For more information, refer to the Timer Clock Characteristics table in the Timer chapter in the Cyclone V Device Handbook, Volume 3.

h2f_l4sp0_interrupt

h2f_l4sp1_interrupt

Enable NAND interrupts Enables the interface for the HPS NAND controller interrupt to the FPGA

h2f_nand_interrupt

Enable OSC timer interrupts Enables interface for the HPS OSC timer interrupt to the FPGA. For more information, refer to the Timer Clock Characteristics table in the Timer chapter in the Cyclone V Device Handbook, Volume 3.

h2f_osc0_interrupt

h2f_osc1_interrupt

Enable Quad SPI interrupts Enables interface for the HPS QSPI controller interrupt to the FPGA

h2f_qspi_interrupt

Enable SD/MMC interrupts Enables the interface for the HPS SD/MMC controller interrupt to the FPGA

h2f_sdmmc_interrupt

Enable SPI master interrupts Enables the interface for the HPS SPI master controller interrupt to the FPGA

h2f_spi0_interrupt

h2f_spi1_interrupt

Enable SPI slave interrupts Enables the interface for the HPS SPI slave controller interrupt to the FPGA

h2f_spi2_interrupt

h2f_spi3_interrupt

Enable UART interrupts Enables the interface for the HPS UART controller interrupt to the FPGA

h2f_uart0_interrupt

h2f_uart1_interrupt

Enable USB interrupts Enables the interface for the HPS USB controller interrupt to the FPGA

h2f_usb0_interrupt

h2f_usb1_interrupt

Enable watchdog interrupts Enables the interface for the HPS watchdog interrupt to the FPGA

h2f_wdog0_interrupt

h2f_wdog1_interrupt