Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

A.7.2. Partial Reconfiguration

Partial reconfiguration allows you to reconfigure part of the device while other sections remain running. The HPS performs partial reconfiguration while the FPGA portion of the device is in user mode. The following sequence suggests one way for software to perform a partial configuration:

  • If PR_READY=1, continue to step 7.
  • If PR_READY is 0, then go back and repeat step 5. Note that a minimum of 16 DCLK pulses are required.

If the HPS resets in the middle of a partial reconfiguration, software can assume that the configuration is unsuccessful. After an HPS warm reset, software must repeat the steps for partial configuration. After an HPS cold reset, software must repeat the steps for Full Configuration.

  1. Read the mode bit of the stat register in fpgamgrregs to ensure that the FPGA is in user mode.
  2. Set the cdratio bit of the ctrl register to match the characteristics of the partial reconfiguration image and set the cfgwdth bit of the ctrl register to 0 for 16-bit configuration data width.
  3. Set the en bit of the ctrl register to 1 to give the FPGA manager control of the configuration input signals.
  4. Set the prreq bit of the ctrl register to 1 to assert PR_REQUEST.
  5. Write a value of 1 to the dclkcnt register to generate DCLK pulses for one clock cycle.
  6. Poll the fpgamgrregs.mon registers to observe the PR_READY (prr) bit.
  7. Write a value of 3 to the dclkcnt register to generate DCLK pulses for three clock cycles.
  8. Set the axicfgen bit of the ctrl register to 1 to enable sending configuration data to the FPGA.
  9. Write the partial reconfiguration image to the data register in the FPGA manager fpgamgrdata registers. You can also choose to use a DMA to transfer the configuration image from a peripheral device to the FPGA manager.
  10. Poll the fpgamgrregs.mon registers to observe the PR_DONE (prd), PR_READY (prr), PR_ERROR (pre), and CRC_ERROR (crc) bits until the bits match one of the completion statuses shown in Table A–12.
  11. Set the axicfgen bit of the ctrl register to 0 to disable sending configuration data to the FPGA.
  12. Set the prreq bit of the ctrl register to 0 to deassert PR_REQUEST.
  13. Write a value of 128 to the dclkcnt register to generate DCLK pulses for 128 clock cycles.
  14. Poll the dcntdone bit of the dclkstat register until it changes to 1, which indicates that all the DCLKs have been sent.
  15. Write a 1 to the dcntdone bit of the dclkstat register to clear the completed status flag.
  16. Poll the fpgamgrregs.mon registers to observe the PR_DONE (prd), PR_READY (prr), PR_ERROR (pre), and CRC_ERROR (crc) bits. When all bits are set to 0, the FPGA is ready for the next transaction.
  17. Set the en bit of the ctrl register to 0 to allow the external pins to drive the configuration input signals.