Cyclone® V Hard Processor System Technical Reference Manual

ID 683126
Date 8/28/2023
Public
Document Table of Contents

9.3.5.1. FPGA-to-HPS Bridge Clocks and Resets

The master interface of the bridge in the HPS logic operates in the l3_main_clk clock domain. The slave interface exposed to the FPGA fabric operates in the f2h_axi_clk clock domain provided by the user logic. The bridge provides clock crossing logic that allows the logic in the FPGA to operate in any clock domain, asynchronous from the HPS.

The FPGA-to-HPS bridge has one reset signal, fpga2hps_bridge_rst_n. The reset manager drives this signal to the FPGA-to-HPS bridge on a cold or warm reset.