Intel® Cyclone® 10 LP Device Datasheet

ID 683251
Date 10/31/2022
Public
Document Table of Contents

FPP Configuration Timing

Table 41.  FPP Timing Parameters for Intel® Cyclone® 10 LP Devices
Symbol Parameter Minimum Maximum Unit
1.2 V Core Voltage 1.0 V Core Voltage 1.2 V Core Voltage 1.0 V Core Voltage
tCF2CD nCONFIG low to CONF_DONE low 500 ns
tCF2ST0 nCONFIG low to nSTATUS low 500 ns
tCFG nCONFIG low pulse width 500 ns
tSTATUS nSTATUS low pulse width 45 230 54 µs
tCF2ST1 nCONFIG high to nSTATUS high 230 55 µs
tCF2CK nCONFIG high to first rising edge on DCLK 230 54 µs
tST2CK nSTATUS high to first rising edge of DCLK 2 µs
tDH Data hold time after rising edge on DCLK 0 ns
tCD2UM CONF_DONE high to user mode 56 300 650 µs
tCD2CU CONF_DONE high to CLKUSR enabled 4 × maximum DCLK period
tCD2UMC CONF_DONE high to user mode with CLKUSR option on tCD2CU + (3,192 × CLKUSR period)
tDSU Data setup time before rising edge on DCLK 5 8 ns
tCH DCLK high time 3.2 6.4 ns
tCL DCLK low time 3.2 6.4 ns
tCLK DCLK period 7.5 15 ns
fMAX DCLK frequency 133 66 MHz
54 This value is applicable if you do not delay configuration by extending the nCONFIG or nSTATUS low pulse width.
55 This value is applicable if you do not delay configuration by externally holding the nSTATUS low.
56 The minimum and maximum numbers apply only if you choose the internal oscillator as the clock source for starting the device.