Intel® Cyclone® 10 LP Device Datasheet

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ID 683251
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Cyclone® 10 LP Device Datasheet
Intel® Cyclone® 10 LP Device Datasheet x
Operating Conditions Power Consumption Switching Characteristics Configuration Specifications I/O Timing Glossary Document Revision History for the Intel® Cyclone® 10 LP Device Datasheet
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot or Undershoot Voltage Recommended Operating Conditions ESD Performance DC Characteristics I/O Standard Specifications
DC Characteristics x
Supply Current Bus Hold OCT Specifications Pin Capacitance Internal Weak Pull-Up and Weak Pull-Down Resistor Hot-Socketing Schmitt Trigger Input
I/O Standard Specifications x
Single-Ended I/O Standard Specifications Single-Ended SSTL and HSTL I/O Reference Voltage Specifications Single-Ended SSTL and HSTL I/O Standards Signal Specifications Differential SSTL I/O Standard Specifications Differential HSTL I/O Standard Specifications Differential I/O Standard Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance
Core Performance Specifications x
Clock Tree Specifications PLL Specifications Embedded Multiplier Specifications Memory Block Specifications
Periphery Performance x
High-Speed I/O Specifications Duty Cycle Distortion Specifications OCT Calibration Timing Specification IOE Programmable Delay
High-Speed I/O Specifications x
RSDS Transmitter Timing Specifications Emulated RSDS_E_1R Transmitter Timing Specifications Mini-LVDS Transmitter Timing Specifications True LVDS Transmitter Timing Specifications Emulated LVDS Transmitter Timing Specifications LVDS Receiver Timing Specifications
Configuration Specifications x
JTAG Timing Parameters Active Configuration Mode Specifications AS Configuration Timing Passive Configuration Mode Specifications PS Configuration Timing FPP Configuration Timing
Intel® Cyclone® 10 LP Device Datasheet

Internal Weak Pull-Up and Weak Pull-Down Resistor

Table 11.  Internal Weak Pull-Up and Weak Pull-Down Resistor Values for Cyclone 10 DevicesAll I/O pins have an option to enable weak pull-up except the configuration, test, and JTAG pins. The weak pull-down feature is only available for JTAG TCK pin.
Symbol Parameter Condition Min Typ Max Unit
R_PU Value of the I/O pin pull-up resistor before and during configuration, as well as user mode if you enable the programmable pull-up resistor option VCCIO = 3.3 V ± 5% 21 22 7 25 41 kΩ
VCCIO = 3.0 V ± 5% 21 22 7 28 47 kΩ
VCCIO = 2.5 V ± 5% 21 22 8 35 61 kΩ
VCCIO = 1.8 V ± 5% 21 22 10 57 108 kΩ
VCCIO = 1.5 V ± 5% 21 22 13 82 163 kΩ
VCCIO = 1.2 V ± 5% 21 22 19 143 351 kΩ
R_PD Value of the I/O pin pull-down resistor before and during configuration VCCIO = 3.3 V ± 5%  23 6 19 30 kΩ
VCCIO = 3.0 V ± 5% 23 6 22 36 kΩ
VCCIO = 2.5 V ± 5% 23 6 25 43 kΩ
VCCIO = 1.8 V ± 5% 23 7 35 71 kΩ
VCCIO = 1.5 V ± 5% 23 8 50 112 kΩ
21 Pin pull-up resistance values may be lower if an external source drives the pin higher than VCCIO.
22 R_PU = (VCCIO – VI)/IR_PU
Minimum condition: –40°C; VCCIO  = VCC + 5% , VI  = VCC + 5%  – 50 mV;
Typical condition: 25°C; VCCIO  = VCC, VI  = 0 V;
Maximum condition: 100°C; VCCIO  = VCC – 5% , VI  = 0 V; in which VI  refers to the input voltage at the I/O pin.
23 R_PD = VI/IR_PD
Minimum condition: –40°C; VCCIO  = VCC + 5% , VI  = 50 mV;
Typical condition: 25°C; VCCIO  = VCC, VI  = VCC – 5% ;
Maximum condition: 100°C; VCCIO  = VCC – 5% , VI  = VCC – 5% ; in which VI  refers to the input voltage at the I/O pin.
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