Intel® Cyclone® 10 LP Device Datasheet

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ID 683251
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
Intel® Cyclone® 10 LP Device Datasheet
Intel® Cyclone® 10 LP Device Datasheet x
Operating Conditions Power Consumption Switching Characteristics Configuration Specifications I/O Timing Glossary Document Revision History for the Intel® Cyclone® 10 LP Device Datasheet
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot or Undershoot Voltage Recommended Operating Conditions ESD Performance DC Characteristics I/O Standard Specifications
DC Characteristics x
Supply Current Bus Hold OCT Specifications Pin Capacitance Internal Weak Pull-Up and Weak Pull-Down Resistor Hot-Socketing Schmitt Trigger Input
I/O Standard Specifications x
Single-Ended I/O Standard Specifications Single-Ended SSTL and HSTL I/O Reference Voltage Specifications Single-Ended SSTL and HSTL I/O Standards Signal Specifications Differential SSTL I/O Standard Specifications Differential HSTL I/O Standard Specifications Differential I/O Standard Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance
Core Performance Specifications x
Clock Tree Specifications PLL Specifications Embedded Multiplier Specifications Memory Block Specifications
Periphery Performance x
High-Speed I/O Specifications Duty Cycle Distortion Specifications OCT Calibration Timing Specification IOE Programmable Delay
High-Speed I/O Specifications x
RSDS Transmitter Timing Specifications Emulated RSDS_E_1R Transmitter Timing Specifications Mini-LVDS Transmitter Timing Specifications True LVDS Transmitter Timing Specifications Emulated LVDS Transmitter Timing Specifications LVDS Receiver Timing Specifications
Configuration Specifications x
JTAG Timing Parameters Active Configuration Mode Specifications AS Configuration Timing Passive Configuration Mode Specifications PS Configuration Timing FPP Configuration Timing
Intel® Cyclone® 10 LP Device Datasheet

Pin Capacitance

Table 10.  Pin Capacitance for Intel® Cyclone® 10 LP Devices
Symbol Parameter Typical – Quad Flat Pack (QFP) Typical – Ball-Grid Array (BGA) 18 Unit
CIOTB Input capacitance on top and bottom I/O pins 7 6 pF
CIOLR Input capacitance on right I/O pins 7 5 pF
CLVDSLR Input capacitance on right I/O pins with dedicated LVDS output 8 7 pF
CVREFLR 19 Input capacitance on right dual-purpose VREF pin when used as VREF or user I/O pin 21 21 pF
CVREFTB 19 Input capacitance on top and bottom dual-purpose VREF pin when used as VREF or user I/O pin 23 20 23 pF
CCLKTB Input capacitance on top and bottom dedicated clock input pins 7 6 pF
CCLKLR Input capacitance on right dedicated clock input pins 6 5 pF
18 The pin capacitance applies to FBGA, UBGA, and MBGA packages.
19 When you use the VREF pin as a regular input or output, you can expect a reduced performance of toggle rate and tCO because of higher pin capacitance.
20 CVREFTB for the 10CL025 device is 30 pF.
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