Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

A.4.3. Boot Select

The boot select (BSEL) pins offer multiple methods to obtain the preloader image. On a cold reset or when a RAM boot has not been requested, the user asserts the BSEL pins on the device to indicate the boot source that is required. These pins are sampled on deassertion of cold reset and are written to the bootinfo register in the System Manager. The value of this register is read during boot ROM execution so that the appropriate interface pins can be initialized. If the boot source is from FPGA, the bsel field value reads as 0x1 in the bootinfo register and no HPS interface is configured for external boot.

Note: The acronyms BSEL and BOOTSEL are used interchangeably to define the boot select pins.
Table 256.  BSEL Values for Boot Source Selection

BSEL[2:0] Value

Flash Device

0x0

Reserved

0x1

FPGA (HPS-to-FPGA bridge)

0x2

1.8 V NAND flash memory

0x3

3.3 V NAND flash memory

0x4

1.8 V SD/MMC flash memory with external transceiver

0x5

3.3 V SD/MMC flash memory with internal transceiver

0x6

1.8 V quad SPI flash memory

0x7

3.3 V quad SPI flash memory

Note: If the BSEL value is set to 0x4 or 0x5, an external translation transceiver may be required to supply level-shifting and isolation if the SD cards interfacing to the SD/MMC controller must operate at a different voltage than the controller interface. Please refer to the SD/MMC Controller chapter for more information.

The HPS flash sources can store various file types, such as:

  • FPGA programming files
  • Preloader binary file (up to four copies)
  • Boot loader binary file
  • Operating system binary files
  • Application file system

When BSEL = 0x1, the boot source is the FPGA and the CSEL pins are ignored. PLLs are bypassed so that OSC1 drives all the clocks.

If an HPS flash interface has been selected to load the boot image, then the boot ROM enables and configures that interface before loading the boot image into on-chip RAM, verifying it and passing software control to the preloader.

If the external RAM boot source is invalid or if the boot ROM code cannot find a valid image in flash, then the boot ROM code checks to see if there is a fallback image in the FPGA. If there is then the boot ROM executes that.

If the FPGA fabric is the boot source, the boot ROM code waits until the FPGA portion of the device is in user mode, and is ready to execute code and then passes software control to the preloader in the FPGA RAM.