Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

22.3.2. FPGA Routing

Table 208.  Signals for FPGA Routing

Signal

Width

Direction

Description

uart_rxd

1 bit

Input

Serial input

uart_txd

1 bit

Output

Serial output

uart_cts

1 bit

Input

Clear to send

uart_rts

1 bit

Output

Request to send

uart_dsr

1 bit

Input

Data set ready

uart_dcd

1 bit

Input

Data carrier detect

uart_ri

1 bit

Input

Ring indicator

uart_dtr

1 bit

Output

Data terminal ready

uart_out1_n

1 bit

Output

User defined output 1

uart_out2_n

1 bit

Output

User defined output 2