Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

3.3.3. Clock Groups

The clock manager contains one clock group for each PLL and one clock group for the HPS_CLK1 pin.

HPS_CLK1 and HPS_CLK2 are powered by the HPS reset and clock input pins power supply (VCCRSTCLK_HPS). For more information on VCCRSTCLK_HPS refer to the Arria V Device Datasheet.