Arria V Hard Processor System Technical Reference Manual

ID 683011
Date 12/02/2022
Public
Document Table of Contents

2.1. Features of the HPS

The main modules of the HPS are:

  • MPU subsystem featuring a dual-core Arm* Cortex®-A9 MPCore processor
  • General-purpose direct memory access (DMA) controller
  • Two Ethernet media access controllers (EMACs)
  • Two USB 2.0 on-the-go (OTG) controllers
  • NAND flash controller
  • Quad SPI flash controller
  • Secure digital/multimedia card (SD/MMC) controller
  • Two serial peripheral interface (SPI) master controllers
  • Two SPI slave controllers
  • Four inter-integrated circuit (I2C) controllers1
  • 64 KB on-chip RAM
  • 64 KB on-chip boot ROM
  • Two UARTs
  • Four timers
  • Two watchdog timers
  • Three general-purpose I/O (GPIO) interfaces
  • Arm* CoreSight* debug components:
    • Debug access port (DAP)
    • Trace port interface unit (TPIU)
    • System trace macrocell (STM)
    • Program trace macrocell (PTM)
    • Embedded trace router (ETR)
    • Embedded cross trigger (ECT)
  • System manager
  • Clock manager
  • Reset manager
  • Scan manager
  • FPGA manager
  • SDRAM controller subsystem
1 Two of the four I2Cs, provide support for general purpose.