Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 4/02/2022
Public

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Document Table of Contents

9.3. Component Interface Tcl Reference Revision History

The table below indicates edits made to the Component Interface Tcl Reference content since its creation:

Document Version Intel® Quartus® Prime Version Changes
2021.03.29 21.1
  • Converted to "host" and "agent" inclusive terminology for Avalon® memory mapped interface descriptions and related GUI elements throughout.
2019.04.01 19.1.0
  • Described new domain and post adaptation assignments in "Interconnect Parameters" topic.
2018.09.24 18.1.0
  • Added new _hw.tcl interface properties that allow importing and exporting register maps in IP-XACT format.
2018.05.07 18.0.0
  • Added wire-level expression commands to support wire-level interfaces.
  • Updated send_message level availability for INFO messages.
  • Updated set_port_property availability.
2017.11.06 17.1.0
  • Changed instances of Qsys Pro to Platform Designer
  • Added statement clarifying use of brackets.
  • Added properties and interface commands to support SystemVerilog.
2016.10.31 16.1.0
  • Implemented Intel rebranding.
  • Implemented Qsys rebranding.
2015.11.02 15.1.0 Changed instances of Quartus II to Quartus Prime.
2015.05.04 15.0.0 Edit to add_fileset_file command.
December 2014 14.1.0
  • set_interface_upgrade_map
  • Moved Port Roles (Interface Signal Types) section to Qsys Interconnect.
November 2013 13.1.0
  • add_hdl_instance
May 2013 13.0.0
  • Consolidated content from other Qsys chapters.
  • Added AMBA APB support.
November 2012 12.1.0
  • Added the demo_axi_memory example with screen shots and example _hw.tcl code.
June 2012 12.0.0
  • Added AXI 3 support.
  • Added: set_display_item_property, set_parameter_property,LONG_DESCRIPTION, and static filesets.
November 2011 11.1.0
  • Template update.
  • Added: set_qip_strings, get_qip_strings, get_device_family_displayname, check_device_family_equivalence.
May 2011 11.0.0
  • Revised section describing HDL and composed component implementations.
  • Separated reset and clock interfaces in example.
  • Added: TRISTATECONDUIT_INFO, GENERATION_ID, UNIQUE_ID SYSTEM_INFO.
  • Added: WIDTH and SYSTEM_INFO_ARG parameter properties.
  • Removed the doc_type argument from the add_documentation_link command.
  • Removed: get_instance_parameter_properties
  • Added: add_fileset, add_fileset_file, create_temp_file.
  • Updated Tcl examples to show separate clock and reset interfaces.
December 2010 10.1.0
  • Initial release.