Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 4/02/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5.5.4.2. Limited Concurrency

Placing a bridge between multiple host and agent interfaces limits the number of concurrent transfers your system can initiate. This limitation is the same when connecting multiple host interfaces to a single agent interface. The agent interface of the bridge is shared by all the hosts and, as a result, Platform Designer creates arbitration logic. If the components placed behind a bridge are infrequently accessed, this concurrency limitation may be acceptable.

Bridges can have a negative impact on system performance if you use them inappropriately. For example, if multiple memories are used by several hosts, you should not place the memory components behind a bridge. The bridge limits memory performance by preventing concurrent memory accesses. Placing multiple memory components behind a bridge can cause the separate agent interfaces to appear as one large memory to the hosts accessing the bridge; all hosts must access the same agent interface.

Figure 128. Inappropriate Use of a Bridge in a Hierarchical System

A memory subsystem with one bridge that acts as a single agent interface for the Avalon® memory mapped Nios® II and DMA hosts, which results in a bottleneck architecture. The bridge acts as a bottleneck between the two hosts and the memories.

If the fMAX of your memory interfaces is low and you want to use a pipeline bridge between subsystems, you can place each memory behind its own bridge, which increases the fMAX of the system without sacrificing concurrency.

Figure 129. Efficient Memory Pipelining Without a Bottleneck in a Hierarchical System