Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 4/02/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.6.4.1. Reset Sequencer Parameters

Table 84.  Reset Sequencer Parameters
Parameter Description
Number of reset outputs Sets the number of output resets to be sequenced, which is the number of output reset signals defined in the component with a range of 2 to 10.
Number of reset inputs Sets the number of input reset signals to be sequenced, which is the number of input reset signals defined in the component with a range of 1 to 10.
Minimum reset assertion time Specifies the minimum assertion cycles between the assertion of the last sequenced reset, and the deassertion of the first sequenced reset. The range is 0 to 1023.
Enable Reset Sequencer CSR Enables CSR functionality of the Reset Sequencer through an Avalon® interface.
reset_out# Lists the reset output signals. Set the parameters in the other columns for each reset signal in the table.
ASRT Seq# Determines the order of reset assertion. Enter the values 1, 2, 3, etc. to specify the required non-overlapping assertion order. This value determines the ASRT_REMAP value in the component HDL.
ASRT Cycle# Number of cycles to wait before assertion of the reset. The value set here corresponds to the ASRT_DELAY value in the component HDL. The range is 0 to 1023.
DSRT Seq# Determines the reset order of reset deassertion. Enter the values 1, 2, 3, etc. to specify the required non-overlapping deassertion order. This value determines the DSRT_REMAP value in the component HDL.
DSRT Cycle#/Deglitch# Number of cycles to wait before deasserting or deglitching the reset. If the USE_DRST_QUAL parameter is set to 0, specifies the number of cycles to wait before deasserting the reset. If USE_DSRT_QUAL is set to1, specifies the number of cycles to deglitch the input reset_dsrt_qual signal. This value determines either the DSRT_DELAY, or the DSRT_QUALCNT value in the component HDL, depending on the USE_DSRT_QUAL parameter setting. The range is 0 to 1023.
USE_DSRT_QUAL If you set USE_DSRT_QUAL to 1, the deassertion sequence waits for an external input signal for sequence qualification instead of waiting for a fixed delay count. To use a fixed delay count for deassertion, set this parameter to 0.