Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 4/02/2022
Public

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7.11.6. Avalon® Streaming Single-Clock FIFO IP Registers

Table 191.   Avalon® Streaming Single-Clock FIFO IP RegistersThe CSR interface in the Avalon® Streaming Single Clock FIFO IP provides access to registers.

32-Bit Word Offset

Name

Access

Reset

Description

0

fill_level

R

0

24-bit FIFO fill level. Bits 24 to 31 are not used.

1

Reserved

Reserved for future use.

2

almost_full_threshold

RW

FIFO depth–1

Set this register to a value that indicates the FIFO buffer is getting full.

3

almost_empty_threshold

RW

0

Set this register to a value that indicates the FIFO buffer is getting empty.

4

cut_through_threshold

RW

0

0—Enables store and forward mode.

Greater than 0—Enables cut-through mode and specifies the minimum of entries in the FIFO buffer before the valid signal on the Avalon® streaming source interface is asserted. Once the FIFO IP starts sending the data to the downstream component, it continues to do so until the end of the packet.

Note: To turn on Cut-through mode, Use store and forward must be set to 0. Turning on Use store and forward mode prompts the user to turn on Use fill level, and then the CSR appears.

5

drop_on_error

RW

0

0—Disables drop-on error.

1—Enables drop-on error.

This register applies only when the Use packet and Use store and forward parameters are turned on.

Table 192.  Register Description for Avalon® Streaming Dual-Clock FIFO The in_csr and out_csr interfaces in the Avalon® Streaming Dual Clock FIFO IP reports the FIFO fill level.

32-Bit Word Offset

Name

Access

Reset Value

Description

0

fill_level

R

0

24-bit FIFO fill level. Bits 24 to 31 are not used.