Intel® Quartus® Prime Pro Edition User Guide: Platform Designer

ID 683609
Date 4/02/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

6.6.4.3.5. Reset Sequencer Software Sequenced Reset Deassert Control Register

You can program the Software Sequenced Reset Deassert register to control the reset deassertion sequence.

When the corresponding enable bit is set, the sequencer stops when the desired reset asserts, and then sets the Reset Deasserted and waiting for SW to proceed bit. The Reset Sequencer proceeds only after the Reset Deasserted and waiting for SW to proceed bit is cleared.

Table 90.  Values for the Reset Sequencer Software Sequenced Reset Deassert Control Register at Offset 0x10
Bit Attribute Default Description
31:10 Reserved.
9:0 RW 0x3FF Per-reset SW sequenced reset deassert enable—This is a per-bit enable for SW-sequenced reset deassert. If bitN of this register is set, the sequencer sets bit29 of the Status Register when a resetN is asserted. It then waits for the bit29 of the status register to clear before proceeding with the sequence. By default, all bits are enabled (fully SW sequenced).