AN 812: Platform Designer System Design Tutorial

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ID 683855
Date 4/02/2018
Public
Document Table of Contents
Document Table of Contents x
Platform Designer System Design Tutorial
Platform Designer System Design Tutorial x
Hardware and Software Requirements Download and Install the Tutorial Design Files Build the Hardware Design Build Software Applications and Download the Design AN 812: Platform Designer System Design Tutorial Revision History
Build the Hardware Design x
Open the Intel® Quartus® Prime Pro Edition Project Build a Platform Designer System with a Top-Down Approach Implement the Memory Tester Subsystem
Build a Platform Designer System with a Top-Down Approach x
Add a Processor Subsystem to the Top-Level Build the Processor Subsystem Add External Memory Interface Instantiate a Memory Tester Subsystem as a Generic Component Connect and Generate IP Files Examples of Platform Designer Generic Components
Build the Processor Subsystem x
Add a Nios® II Processor Add RAM, JTAG UART, and Avalon-MM Pipeline Bridge Connect cpu_subsystem Components Platform Designer and Platform Designer (Standard) Differences
Implement the Memory Tester Subsystem x
Add Clock, Reset, and Avalon-MM components Add Pre-Built Systems and Memory Test Microcore Components Export Signals, Set Base Address Assignments, and Connect Memory Tester Interface Components Resolve Interface Requirements and Value Mismatches Replace the memory_tester_subsystem Generic Component Synchronize IP Results
Build Software Applications and Download the Design x
Hardware setup Run the Bash Script
Platform Designer System Design Tutorial

Platform Designer and Platform Designer (Standard) Differences

Platform Designer introduces a hierarchical isolation between system interconnect and IP components by saving the parameters of each IP component in a .ip file under <project folder>/ip/<Platform Designer system name> and saving of the system interconnect in a .qsys file under <project folder>. The RTL of each .ip or .qsys file can be generated in isolation as it contains the full information required to reproduce the state of the RTL. There are no unresolved dependencies between files.

For example, Platform Designer saves the Nios® II processor parameterization in <project folder>/ip/cpu_subsystem/cpu_subsystem_ nios2_gen2_0.ip, and the system interconnect in <project folder>/cpu_subsystem.qsys.

Figure 16. File Location for Nios® II Processor IP File
Platform Designer and Platform Designer (Standard) differ also differ in how they handle IP files:
  • Platform Designer requires that you include the .qsys file along with a list of .ip files associated with that Platform Designer project. The Intel® Quartus® Prime Pro Edition software manages this for you after you save your Platform Designer project.
  • The older Platform Designer (Standard) tool saves both component instantiation and system interconnects in a .qsys file. When integrating a Platform Designer (Standard) system to a Intel® Quartus® Prime project, you only need to include a single Intel® Quartus® Prime IP file (.qip).
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