AN 812: Platform Designer System Design Tutorial

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ID 683855
Date 4/02/2018
Public
Document Table of Contents
Document Table of Contents x
Platform Designer System Design Tutorial
Platform Designer System Design Tutorial x
Hardware and Software Requirements Download and Install the Tutorial Design Files Build the Hardware Design Build Software Applications and Download the Design AN 812: Platform Designer System Design Tutorial Revision History
Build the Hardware Design x
Open the Intel® Quartus® Prime Pro Edition Project Build a Platform Designer System with a Top-Down Approach Implement the Memory Tester Subsystem
Build a Platform Designer System with a Top-Down Approach x
Add a Processor Subsystem to the Top-Level Build the Processor Subsystem Add External Memory Interface Instantiate a Memory Tester Subsystem as a Generic Component Connect and Generate IP Files Examples of Platform Designer Generic Components
Build the Processor Subsystem x
Add a Nios® II Processor Add RAM, JTAG UART, and Avalon-MM Pipeline Bridge Connect cpu_subsystem Components Platform Designer and Platform Designer (Standard) Differences
Implement the Memory Tester Subsystem x
Add Clock, Reset, and Avalon-MM components Add Pre-Built Systems and Memory Test Microcore Components Export Signals, Set Base Address Assignments, and Connect Memory Tester Interface Components Resolve Interface Requirements and Value Mismatches Replace the memory_tester_subsystem Generic Component Synchronize IP Results
Build Software Applications and Download the Design x
Hardware setup Run the Bash Script
Platform Designer System Design Tutorial

Build a Platform Designer System with a Top-Down Approach

  1. To launch Platform Designer, click Tools > Platform Designer .
  2. Click the Create new Qsys system button and name the new Platform Designer system top_system.qsys.
    Figure 3. Create New System Dialog Box
  3. Click Create. The resulting system comes pre-populated with a clock bridge and a reset bridge.
  4. Right-click the name of the clock_in component and click Rename. Type ext_clk.
  5. In the parameter editor, change the Explicit clock rate to 100MHz (100,000).
  6. Right-click the name of the reset_in component and click Rename. Type ext_reset.
    Figure 4. Rename the Clock Bridge and Reset Bridge

Section Content
Add a Processor Subsystem to the Top-Level
Build the Processor Subsystem
Add External Memory Interface
Instantiate a Memory Tester Subsystem as a Generic Component
Connect and Generate IP Files
Examples of Platform Designer Generic Components

Level Two Title