AN 812: Platform Designer System Design Tutorial

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ID 683855
Date 4/02/2018
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Document Table of Contents
Document Table of Contents x
Platform Designer System Design Tutorial
Platform Designer System Design Tutorial x
Hardware and Software Requirements Download and Install the Tutorial Design Files Build the Hardware Design Build Software Applications and Download the Design AN 812: Platform Designer System Design Tutorial Revision History
Build the Hardware Design x
Open the Intel® Quartus® Prime Pro Edition Project Build a Platform Designer System with a Top-Down Approach Implement the Memory Tester Subsystem
Build a Platform Designer System with a Top-Down Approach x
Add a Processor Subsystem to the Top-Level Build the Processor Subsystem Add External Memory Interface Instantiate a Memory Tester Subsystem as a Generic Component Connect and Generate IP Files Examples of Platform Designer Generic Components
Build the Processor Subsystem x
Add a Nios® II Processor Add RAM, JTAG UART, and Avalon-MM Pipeline Bridge Connect cpu_subsystem Components Platform Designer and Platform Designer (Standard) Differences
Implement the Memory Tester Subsystem x
Add Clock, Reset, and Avalon-MM components Add Pre-Built Systems and Memory Test Microcore Components Export Signals, Set Base Address Assignments, and Connect Memory Tester Interface Components Resolve Interface Requirements and Value Mismatches Replace the memory_tester_subsystem Generic Component Synchronize IP Results
Build Software Applications and Download the Design x
Hardware setup Run the Bash Script
Platform Designer System Design Tutorial

Connect and Generate IP Files

You can make connections once the component instantiation is complete. Connect the source and target components with the entries in the following table:
Table 4.  Top Level Platform Designer Connections
Source Component/Signal Target Component/Signal
ext_clk/out_clk
  • ext_reset/clk
  • cpu_subsystem/cpu_clk
  • emif_0/pll_ref_clk
ext_reset/out_reset
  • cpu_subsystem/cpu_reset
  • cpu_subsystem/mem_reset
  • memory_test_subsystem/reset
  • emif_0/global_reset_n
cpu_subsystem/master
  • memory_test_subsystem/slave
cpu_subsystem/cpu_jtag_reset
  • cpu_subsystem/cpu_reset
  • cpu_subsystem/mem_reset
  • memory_test_subsystem/reset
  • emif_0/global_reset_n
memory_test_subsystem/read_master
  • emif_0/ctrl_amm_0
memory_test_subsystem/write_master
  • emif_0/ctrl_amm_0
emif_0/emif_usr_clk
  • cpu_subsystem/mem_clk
  • memory_test_subsystem/clk
emif_0/emif_usr_reset_n
  • cpu_subsystem/mem_reset

Compare your completed system to the following figure:

Figure 27. Top Level Platform Designer System Connections

If there are any errors, read the error message and fix the error.

  1. Click File > Save to save the top-level system.
  2. Click Generate > Generate HDL and click Generate to generate RTL for each component, including components in the cpu_subsystem.
  3. Close Platform Designer. New files appear in the in the Project Navigator > Files tab in the Intel® Quartus® Prime project. You must add another file memory_tester_subsystem.v. Adding this provides an empty entity for memory_tester_subsystem so Intel® Quartus® Prime Pro Edition can elaborate the hierarchy.
  4. In the Tasks window, double-click Add/Remove Files in Project to open the Settings dialog box.
  5. To add an empty memory_tester_subsystem.v file, type memory_tester_subsystem.v in the File name box.
  6. Click Add.
    Figure 28. top_system.qsys IP Files
  7. Compile the project by clicking Processing > Start Compilation. If there are any errors, verify that all required files are present, and that you correctly name the exported ports in the Platform Designer system.

After compilation completes successfully, check the Compilation Reports (Processing > Compilation Report) for Logic Resource Usage, I/O Bank Usage, Clock tree. You can also upload the A10.sof file generated during compilation to a board to check the calibration status of the DDR4 RAM. In the top_level.v file, sdram_cal_success, and sdram_cal_fail are connected to LED3 on the board. A green light indicates that calibration was successful. A red light indicates that calibration failed.

This design flow allows you to verify and debug DDR4 RAM calibration, while maintaining the system structure, before finishing the implementation of the memory tester subsystem.

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