External Memory Interfaces Intel® Arria® 10 FPGA IP User Guide

ID 683106
Date 12/19/2023
Public

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4.1.1.23. clks_sharing_slave_in for DDR3

Core clocks sharing slave input interface

Table 31.  Interface: clks_sharing_slave_inInterface type: Conduit
Port Name Direction Description
clks_sharing_slave_in Input This port should be connected to the core clocks sharing master.