External Memory Interfaces Intel® Arria® 10 FPGA IP User Guide

ID 683106
Date 12/19/2023
Public

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4.1.1.2. pll_locked for DDR3

PLL locked signal

Table 10.  Interface: pll_lockedInterface type: Conduit
Port Name Direction Description
pll_locked Output PLL lock signal to indicate whether the PLL has locked