External Memory Interfaces Intel® Arria® 10 FPGA IP User Guide

ID 683106
Date 12/19/2023
Public

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4.4.17. sideband5

address=48(32 bit)

Field Bit High Bit Low Description Access
mmr_dpd_mps_req 0 0

Deep Power Down/Maximum Power Saving request. Assertion of this bit invokes the deep power down/maximum power saving mode. You should poll for the acknowledge signal. When the acknowledge goes high, it indicates that the system has entered deep power down/maximum power saving mode. You may de-assert this bit to exit deep power down/maximum power saving mode, or keep this bit asserted to maintain deep power down/maximum power saving mode.

Read/Write