Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/31/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Space Converter Intel® FPGA IP 21. Defective Pixel Correction Intel® FPGA IP 22. Deinterlacer Intel® FPGA IP 23. Demosaic Intel® FPGA IP 24. FIR Filter Intel® FPGA IP 25. Frame Cleaner Intel® FPGA IP 26. Full-Raster to Clocked Video Converter Intel® FPGA IP 27. Full-Raster to Streaming Converter Intel® FPGA IP 28. Genlock Controller Intel® FPGA IP 29. Generic Crosspoint Intel® FPGA IP 30. Genlock Signal Router Intel® FPGA IP 31. Guard Bands Intel® FPGA IP 32. Histogram Statistics Intel® FPGA IP 33. Interlacer Intel® FPGA IP 34. Mixer Intel® FPGA IP 35. Pixels in Parallel Converter Intel® FPGA IP 36. Scaler Intel® FPGA IP 37. Stream Cleaner Intel® FPGA IP 38. Switch Intel® FPGA IP 39. Tone Mapping Operator Intel® FPGA IP 40. Test Pattern Generator Intel® FPGA IP 41. Unsharp Mask Intel® FPGA IP 42. Video and Vision Monitor Intel FPGA IP 43. Video Frame Buffer Intel® FPGA IP 44. Video Frame Reader Intel FPGA IP 45. Video Frame Writer Intel FPGA IP 46. Video Streaming FIFO Intel® FPGA IP 47. Video Timing Generator Intel® FPGA IP 48. Vignette Correction Intel® FPGA IP 49. Warp Intel® FPGA IP 50. White Balance Correction Intel® FPGA IP 51. White Balance Statistics Intel® FPGA IP 52. Design Security 53. Document Revision History for Video and Vision Processing Suite User Guide

8.4. 1D LUT IP Registers

Each register is either read-only (RO), read-write (RW) or write-only (WO).
Table 37.  1D LUT IP RegistersIn the software API the register names appear with a prefix of INTEL_VVP, INTEL_VVP_CORE or INTEL_VVP_1DLUT as appropriate and with an optional REG suffix.
Address Register Access Description
Lite 9 Full
Parameterization registers
0x0000 VID_PID RO N/A

Read this register to retrieve the ID of the 1D LUT IP.

This register always returns 0x6FA7_017D.

0x0004 VERSION RO N/A Read this register to retrieve the version information for the 1D LUT IP.
0x0008 LITE_MODE RO N/A

Read this register to determine if lite mode is on.

This register always returns 1.

0x000C DEBUG_ENABLED RO N/A

Read this register to determine if Debug features are on.

This register returns 0 for off and 1 for on.

0x0010 BPS_IN RO N/A Read this register to determine the bits per symbol for the input data.
0x0014 BPS_OUT RO N/A Read this register to determine the bits per symbol for the output data.
0x0018 NUM_COLOR RO N/A Read this register to determine the number of color planes.
0x001C PIP RO N/A Read this register to determine the number of pixels in parallel.
0x0020 MAX_WIDTH RO N/A Read this register to determine the maximum supported input field width.
0x0024 MAX_HEIGHT RO N/A Read this register to determine the maximum supported input field height.
0x0028 EQUIDISTANT RO N/A Read this register to determine if Equidistant LUT Entries are on.
0x002C BITS_LUT RO N/A Read this register to determine the number of maximum bits to address the whole LUT.
0x0030 BITS_SEG RO N/A Read this register to determine the number of bits allocated for address bits of each LUT segment. Only relevant if Equidistant LUT Entries are off.
0x0034 BITS_STEP RO N/A Read this register to determine the number of bits allocated as a sparsity factor across segments. Only relevant if Equidistant LUT Entries are off.
0x0038 REVERSE_LUT RO N/A Read this register to determine if the LUT entries and their readouts are reversed.
0x003C to 0x011F - - - Reserved
Control, debug, and statistics registers
0x0120 IMG_INFO_WIDTH RW N/A The expected width of the incoming video fields.
0x0124 IMG_INFO_HEIGHT RW N/A The expected height of the incoming video fields.
0x0128 to 0x013F - - - Reserved
0x0140 STATUS RO N/A

Read this register for information about the 1D LUT IP status.

0x0144 FRAME_STATS RO N/A

Read this register for some frame statistics.

0x0148 - - - Reserved
0x014c CONTROL RW N/A

Control bits and fields of 1D LUT IP

0x0150 to 0x01FF - - - Reserved

0x0200

to

0x0200 + 4 x 2BITS_LUT - 1

CP0_LUT[i] 10 WO N/A

LUT entries for color plane 1.

  • [BPS_IN-1:0]: Lower lookup value
  • [2xBPS_IN-1:BPS_IN]: Upper lookup value
  • [31:2xBPS_IN]: Reserved

0x0200 + 4 x 2BITS_LUT

to

0x0200 + 8 x 2BITS_LUT - 1

CP1_LUT[i] 10 WO N/A

LUT entries for color plane 2.

  • [BPS_IN-1:0]: Lower lookup value
  • [2xBPS_IN-1:BPS_IN]: Upper lookup value
  • [31:2xBPS_IN]: Reserved

These registers are reserved or not implemented if the number of color planes is smaller than 2. Reserved if the address is within the range of the memory-mapped control interface, otherwise not implemented.

0x0200 + 8 x 2BITS_LUT

to

0x0200 + 12 x 2BITS_LUT - 1

CP2_LUT[i] 10 WO N/A

LUT entries for color plane 3.

  • [BPS_IN-1:0]: Lower lookup value
  • [2xBPS_IN-1:BPS_IN]: Upper lookup value
  • [31:2xBPS_IN]: Reserved

These registers are reserved or not implemented if the number of color planes is smaller than 3. Reserved if the address is within the range of the memory-mapped control interface, otherwise not implemented.

0x0200 + 12 x 2BITS_LUT

to

0x0200 + 16 x 2BITS_LUT - 1

CP3_LUT[i] 10 WO N/A

LUT entries for color plane 4.

  • [BPS_IN-1:0]: Lower lookup value
  • [2xBPS_IN-1:BPS_IN]: Upper lookup value
  • [31:2xBPS_IN]: Reserved

These registers are reserved or not implemented if the number of color planes is smaller than 4. Reserved if the address is within the range of the memory-mapped control interface, otherwise not implemented.

0x0200 + 16 x 2BITS_LUT

to end of memory

- - - Reserved or not implemented.

Register Bit Descriptions

Table 38.   STATUS
Name Bits Description
Reserved 31:1 Reserved.
Running 0 When 1, the IP is processing data.
Table 39.   FRAME_STATS
Name Bits Description
Reserved 31:8 Reserved.
Checksum 7:0 A simple checksum of the frame.
Table 40.   CONTROL
Name Bits Description
Reserved 31:1 Reserved
Bypass 0 Set to bypass 1D LUT. When set, 1D LUT passes pixel values unprocessed.
9 Registers are RW only if you also turn on Debug features, otherwise they are WO.
10 Index i from 0 to 2 BITS_LUT - 1