Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/31/2023
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Space Converter Intel® FPGA IP 21. Defective Pixel Correction Intel® FPGA IP 22. Deinterlacer Intel® FPGA IP 23. Demosaic Intel® FPGA IP 24. FIR Filter Intel® FPGA IP 25. Frame Cleaner Intel® FPGA IP 26. Full-Raster to Clocked Video Converter Intel® FPGA IP 27. Full-Raster to Streaming Converter Intel® FPGA IP 28. Genlock Controller Intel® FPGA IP 29. Generic Crosspoint Intel® FPGA IP 30. Genlock Signal Router Intel® FPGA IP 31. Guard Bands Intel® FPGA IP 32. Histogram Statistics Intel® FPGA IP 33. Interlacer Intel® FPGA IP 34. Mixer Intel® FPGA IP 35. Pixels in Parallel Converter Intel® FPGA IP 36. Scaler Intel® FPGA IP 37. Stream Cleaner Intel® FPGA IP 38. Switch Intel® FPGA IP 39. Tone Mapping Operator Intel® FPGA IP 40. Test Pattern Generator Intel® FPGA IP 41. Unsharp Mask Intel® FPGA IP 42. Video and Vision Monitor Intel FPGA IP 43. Video Frame Buffer Intel® FPGA IP 44. Video Frame Reader Intel FPGA IP 45. Video Frame Writer Intel FPGA IP 46. Video Streaming FIFO Intel® FPGA IP 47. Video Timing Generator Intel® FPGA IP 48. Vignette Correction Intel® FPGA IP 49. Warp Intel® FPGA IP 50. White Balance Correction Intel® FPGA IP 51. White Balance Statistics Intel® FPGA IP 52. Design Security 53. Document Revision History for Video and Vision Processing Suite User Guide

49.1.2. Warp IP Performance and Resource Utilization

Intel provides resource and utilization data for guidance. The designs target an Intel Arria 10 10AX115N2F40I2LG device or an Intel Agilex® 7 AGIB027R29A1E2V.

For devices other than Intel Agilex® 7 devices, the Warp IP supports clock rates of 300 MHz for the video related clocks axi4s_vid_in_0_clock, axi4s_vid_out_0_clock, and core_clock.

For Intel Agilex® 7 devices, the Warp IP supports clock rates of 600 MHz for the video related clocks axi4s_vid_in_0_clock, axi4s_vid_out_0_clock, and core_clock. This allows a single pixel in parallel, single engine configuration to process UHD frames at 60 fps. The Warp IP also supports a configuration of 2 pixels in parallel with one engine. Your design can process UHD frames at 60 fps on Intel Agilex® 7 devices with a reduced video clock rate of 300 MHz on the video input and output connections and running the main processing clock at 600 MHz.

Table 934.   HD frame processing on Intel Arria 10 Device with Double Memory BounceProcessing frames of up to 1920x1080 resolution. Intel set the video related clocks axi4s_vid_in_0_clock, axi4s_vid_out_0_clock, and core_clock to a minimum of 150 MHz to allow the IP to process 60 fps. Set these clocks to 300 MHz for frame rates of 120 fps.
Pixel in Parallel Use Single Memory Bounce Number of Engines Max Video Width 149 150 Memory Buffer Size ALMs Memory Blocks (M20K) DSP Blocks
1 Off 1 2048 HD ~6,000 191 36
Table 935.  HD frame processing on Intel Arria 10 Device with Single Memory BounceProcessing frames of up to 1920x1080 resolution. Intel set the video related clocksaxi4s_vid_in_0_clock, axi4s_vid_out_0_clock,and core_clockto a minimum of 150 MHz to allow the IP to process 60 fps. Set these clocks to 300 MHz for frame rates of 120 fps.
Pixel in Parallel Use Single Memory Bounce Cache Blocks per Engine Number of Engines Maximum Video Width 150 Memory BufferSize ALMs Memory Blocks (M20K) DSP Blocks
1 On 256 1 2048 HD ~6,000 163 36
1 On 512 1 2048 HD ~6,000 211 36
1 On 1024 1 2048 HD ~6,000 307 36
Table 936.   UHD Frames at 30 fps on Intel Arria 10 Device with Double Memory Bounce Processing frames of up to 3840x2160 resolution at 30 fps. Intel set the video related clocks axi4s_vid_in_0_clock, axi4s_vid_out_0_clock, and core_clock to 300 MHz.
Pixel in parallel Use Single Memory Bounce Number of Engines Max Video Width 150 Memory Buffer Size ALMs Memory Blocks (M20K) DSP Blocks
1 Off 1 3840 UHD ~6,000 273 36
Table 937.  UHD Frames at 60 fps on Intel Arria 10 Device with Double Memory BounceProcessing frames of up to 3840x2160 resolution at 60 fps. Intel set the video related clocks axi4s_vid_in_0_clock, axi4s_vid_out_0_clock, and core_clock to 300 MHz.
Pixel in parallel Use Single Memory Bounce Number of Engines Max Video Width150 Memory Buffer Size ALMs Memory Blocks (M20K) DSP Blocks
2 Off 2 3840 UHD ~10,000 354 72
Table 938.  UHD frames at 60 fps on Intel Arria 10 Device with Single Memory BounceProcessing frames of up to 3840x2160 resolution at 60 fps. Intel set the video related clocks axi4s_vid_in_0_clock,axi4s_vid_out_0_clock,and core_clock to 300 MHz.
Pixel in parallel Use Single Memory Bounce Cache Blocks per Engine Number of Engines Max Video Width 150 Memory BufferSize ALMs Memory Blocks (M20K) DSP Blocks
2 On 256 2 3840 UHD ~10,000 300 72
2 On 512 2 3840 UHD ~10,000 396 72
2 On 1024 2 3840 UHD ~10,000 588 72
Table 939.   One Pixel In Parallel UHD Frames at 60 fps, on Intel Agilex® 7 Device with Double Memory Bounce

Processing frames of up to 3840x2160 resolution at 60 fps. Intel set the video related clocks axi4s_vid_in_0_clock,axi4s_vid_out_0_clock,and core_clock to 600 MHz. .

Pixel in parallel Use Single Memory Bounce Number of Engines Max Video Width 150 Memory Buffer Size ALMs Memory Blocks (M20K) DSP Blocks
1 Off 1 3840 UHD ~8,000 249 36

Table 940.  One Pixel In Parallel UHD Frames at 60 fps on Intel Agilex® 7 Device with Single Memory BounceProcessing frames of up to 3840x2160 resolution at 60 fps. Intel set the video related clocks axi4s_vid_in_0_clock,axi4s_vid_out_0_clock,andcore_clock to 600 MHz.
Pixel in parallel Use Single Memory Bounce Cache Blocks per Engine Number of Engines Max Video Width 150 Memory Buffer Size ALMs Memory Blocks (M20K) DSP Blocks
1 On 256 1 3840 UHD ~7,000 212 36
1 On 512 1 3840 UHD ~7,000 260 36
1 On 1024 1 3840 UHD ~79,000 356 36
Table 941.   One Pixel In Parallel HD frame processing with Use easy warp on Intel Arria 10 Device

Processing frames of up to 1920x1080 resolution. Intel set the video related clocks axi4s_vid_in_0_clock,axi4s_vid_out_0_clock, and core_clock to a minimum of 150 MHz to allow the IP to process 60 fps. Set these clocks to 300 MHz for frame rates of 120 fps.

Pixel in parallel Maximum Video Width 150 Memory Buffer Size Use Easy Warp ALMs Memory Blocks (M20K) DSP Blocks
1 2048 HD On ~3,000 148 0
Table 942.  One Pixel In Parallel UHD frame processing with Use easy warp on Intel Arria 10 Device  Processing frames of up to 3840 × 2160 resolution. Intel set the video related clocks axi4s_vid_in_0_clock, axi4s_vid_out_0_clock, and core_clock to a minimum of 300 MHz to allow the IP to process 30 fps.
Pixel in parallel Maximum Video Width 150 Memory Buffer Size Use Easy Warp ALMs Memory Blocks (M20K) DSP Blocks
1 3840 UHD On

~3000

271 0
Table 943.  Two Pixels In Parallel UHD frame processing with Use easy warp on Intel Arria 10 Device  Processing frames of up to 3840 × 2160 resolution. Intel set the video related clocks axi4s_vid_in_0_clock, axi4s_vid_out_0_clock, and core_clock to a minimum of 300 MHz to allow the IP to process 60 fps. 
Pixel in parallel Easy Warp Maximum Video Width 150 Use Easy Warp Memory Buffer Size ALMs Memory Blocks (M20K) DSP Blocks
2 1 3840 On UHD

~3000

271 0
149 Same maximum video width for input and output.
150 Same maximum video width for input and output.