Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/31/2023
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Space Converter Intel® FPGA IP 21. Defective Pixel Correction Intel® FPGA IP 22. Deinterlacer Intel® FPGA IP 23. Demosaic Intel® FPGA IP 24. FIR Filter Intel® FPGA IP 25. Frame Cleaner Intel® FPGA IP 26. Full-Raster to Clocked Video Converter Intel® FPGA IP 27. Full-Raster to Streaming Converter Intel® FPGA IP 28. Genlock Controller Intel® FPGA IP 29. Generic Crosspoint Intel® FPGA IP 30. Genlock Signal Router Intel® FPGA IP 31. Guard Bands Intel® FPGA IP 32. Histogram Statistics Intel® FPGA IP 33. Interlacer Intel® FPGA IP 34. Mixer Intel® FPGA IP 35. Pixels in Parallel Converter Intel® FPGA IP 36. Scaler Intel® FPGA IP 37. Stream Cleaner Intel® FPGA IP 38. Switch Intel® FPGA IP 39. Tone Mapping Operator Intel® FPGA IP 40. Test Pattern Generator Intel® FPGA IP 41. Unsharp Mask Intel® FPGA IP 42. Video and Vision Monitor Intel FPGA IP 43. Video Frame Buffer Intel® FPGA IP 44. Video Frame Reader Intel FPGA IP 45. Video Frame Writer Intel FPGA IP 46. Video Streaming FIFO Intel® FPGA IP 47. Video Timing Generator Intel® FPGA IP 48. Vignette Correction Intel® FPGA IP 49. Warp Intel® FPGA IP 50. White Balance Correction Intel® FPGA IP 51. White Balance Statistics Intel® FPGA IP 52. Design Security 53. Document Revision History for Video and Vision Processing Suite User Guide

9.5. 3D LUT IP Software API

The IP includes a software driver that configures and controls all the necessary parameters of the IP.
Figure 17. Software driver usage example
intel_vvp_3d_lut_instance lut_0;
ret = intel_vvp_3d_lut_init(&lut_0, (intel_vvp_core_base)LUT_0_BASE);
if (ret == 0)
{
  /* Load LUT buffer 0 by software */
  if (load_3d_lut(&lut_0, 0) == 0)
  {
    /* Enable LUT processing */
    intel_vvp_3d_lut_enable(&lut_0, true);
  }
  else
  {
    printf("Error loading LUT data: %d\n");
  }
}
else
{
  printf("Error initializing lut_0: %d\n", ret);
}

The driver does not include the load function. You have alternative ways to source the LUT entry data. The simplest is from a precompiled structure in the software source code. An example of using this method is:

int load_3d_lut(intel_vvp_3d_lut_instance* instance, uint8_t buffer)
{
  uint16_t r_idx = 0, g_idx = 0, b_idx = 0;
  uint32_t table_idx = 0;
  while (table_idx < ((sizeof(lut_table)/sizeof(uint16_t)) - 4))
  {
    int result = intel_vvp_3d_lut_load(instance, r_idx, g_idx, b_idx, buffer,
        lut_table[table_idx],
        lut_table[table_idx + 1],
        lut_table[table_idx + 2],
        lut_table[table_idx + 3]);
    if (result != 0)
    {
      return result;
    }
    table_idx += 4;
    if (++r_idx == LUT_TABLE_DIMENSION)
    {
      r_idx = 0;
      if (++g_idx == LUT_TABLE_DIMENSION)
      {
        g_idx = 0;
        if (++b_idx == LUT_TABLE_DIMENSION)
        {
          break;
        }
      }
    }
  }
  return 0;
}

In this example, the data is a flat structure containing four elements per LUT entry (4 * lut_dimension³).

The definition for the dimension and data table is:

 
#DEFINE LUT_TABLE_DIMENSION 17
const uint16_t lut_table[] = {
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000,
0x0050, 0x0050, 0x0050, 0x0000,
0x0079, 0x0079, 0x0079, 0x0000,
0x0092, 0x0092, 0x0092, 0x0000,
0x00A6, 0x00A6, 0x00A6, 0x0000,
0x00B9, 0x00B9, 0x00B9, 0x0000,
/* continues… 4913 lines total */
Table 62.  3D LUT IP API referenceThe software driver for 3D LUT IP provides the following API functions.
Name Description
intel_vvp_3d_lut_init Initialize the LUT instance
intel_vvp_3d_lut_enable Enable LUT processing
intel_vvp_3d_lut_buffer_select Select between LUT buffers
intel_vvp_3d_lut_load Load a LUT entry
intel_vvp_3d_lut_get_double_buffered Get double buffered configuration parameter
intel_vvp_3d_lut_get_input_depth Get bit resolution of input streams
intel_vvp_3d_lut_get_lut_alpha_channel Get alpha channel support configuration parameter"
intel_vvp_3d_lut_get_lut_depth Get bit resolution of LUT streams
intel_vvp_3d_lut_get_dimension Get size of LUT
intel_vvp_3d_lut_get_output_depth Get bit resolution of output streams
intel_vvp_3d_lut_get_pixels_per_clock Get number of pixels processed per clock cycle

intel_vvp_3d_lut_init

void intel_vvp_3d_lut_init( intel_vvp_3d_lut_instance* instance, intel_vvp_core_base base);
Description
Initialize a 3D LUT instance
Arguments
instance – pointer to the 3D LUT software driver instance structure
base – pointer to base address of 3D LUT IP
Return Value
Zero on success, negative integer otherwise

intel_vvp_3d_lut_enable

void intel_vvp_3d_lut_enable( intel_vvp_3d_lut_instance* instance, int enable);
Description
Enable LUT processing
Arguments
instance – pointer to the 3D LUT software driver instance structure
enable – enable LUT operation:
  • 0 – Passthrough input stream unchanged
  • 1 – Enable LUT processing
Return Value
None

intel_vvp_3d_lut_buffer_select

int intel_vvp_3d_lut_buffer_select( intel_vvp_3d_lut_instance* instance, uint8_t buffer);
Description
Select between LUT procession buffers (double buffering must be enabled)
Arguments
instance – pointer to the 3D LUT software driver instance structure
buffer – buffer to be selected (0 or 1)
Return Value
  • 0 – operation is successful
  • -1 – buffer parameter is out of range or double buffering is not configured

intel_vvp_3d_lut_load

int intel_vvp_3d_lut_load( intel_vvp_3d_lut_instance* instance, uint16_t r_idx, uint16_t g_idx, uint16_t b_idx, uint8_t buffer, uint16_t r_val, uint16_t g_val, uint16_t b_val, uint16_t a_val);
Description
Load an entry into the LUT table. Parameters specify the indices for the table, and the R/G/B/A value for the table entry.
Arguments
instance – pointer to the 3D LUT software driver instance structure
r_idx - red index. Range 0 to (LUT dimension - 1)
g_idx - green index. Range 0 to (LUT dimension - 1)
b_idx - blue index. Range 0 to (LUT dimension - 1)
buffer - range 0 to 1 (for double buffered configuration)
r_val - red value. Range 0 to (2lut_depth - 1)
g_val - green value. Range 0 to (2lut_depth - 1)
b_val - blue value. Range 0 to (2lut_depth - 1)
a_val - alpha value. LUT alpha must be enabled. If not, value must be set to 0.
Return Value
  • 0 - successful
  • –1 if r_idx/g_idx/b_idx is out of range
  • –2 if buffer parameter is out of range, or double buffering is not configured
  • –3 if alpha value is set and not supported
  • –4 if r_val/g_val/b_val is out of range

intel_vvp_3d_lut_get_double_buffered

uint8_t intel_vvp_3d_lut_get_double_buffered( intel_vvp_3d_lut_instance* instance);
Description
Get double-buffered IP configuration
Arguments
instance – pointer to the 3D LUT software driver instance structure
Return Value
  • 0 if double buffer option is not configured
  • 1 if double buffer option is configured

intel_vvp_3d_lut_get_input_depth

uint8_t intel_vvp_3d_lut_get_input_depth( intel_vvp_3d_lut_instance* instance);
Description
Get bit resolution of input streams
Arguments
instance – pointer to the 3D LUT software driver instance structure
Return Value
Range is 8 to 16. Value is number of bits per input color plane

intel_vvp_3d_lut_get_lut_alpha_channel

uint8_t intel_vvp_3d_lut_get_lut_alpha_channel( intel_vvp_3d_lut_instance* instance);
Description

Get alpha channel support configuration parameter

Arguments
instance – pointer to the 3D LUT software driver instance structure
Return Value
  • 0 if alpha channel is not supported
  • 1 if alpha channel is supported

intel_vvp_3d_lut_get_lut_depth

uint8_t intel_vvp_3d_lut_get_lut_depth( intel_vvp_3d_lut_instance* instance);
Description
Get configured bit resolution of LUT processing streams
Arguments
instance – pointer to the 3D LUT software driver instance structure
Return Value
Range is 8 to 16. Value is number of bits per LUT color plane

intel_vvp_3d_lut_get_dimension

uint8_t intel_vvp_3d_lut_get_dimension( intel_vvp_3d_lut_instance* instance);
Description
Get configured LUT size. Value is single dimension size. A dimension size of A gives a LUT size of (A x A x A) entries
Arguments
instance – pointer to the 3D LUT software driver instance structure
Return Value
Valid values are {9, 17, 33, 65}

intel_vvp_3d_lut_get_output_depth

uint8_t intel_vvp_3d_lut_get_output_depth( intel_vvp_3d_lut_instance* instance);
Description
Get bit resolution of LUT output streams
Arguments
instance – pointer to the 3D LUT software driver instance structure
Return Value
Range is 8 to 16. Value is number of bits per output color plane

intel_vvp_3d_lut_get_pixels_per_clock

uint8_t intel_vvp_3d_lut_get_pixels_per_clock( intel_vvp_3d_lut_instance* instance);
Description
Number of input pixels processed for each video clock cycle
Arguments
instance – pointer to the 3D LUT software driver instance structure
Return Value
Number of pixels. Range is 1 to 8.