Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/31/2023
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Space Converter Intel® FPGA IP 21. Defective Pixel Correction Intel® FPGA IP 22. Deinterlacer Intel® FPGA IP 23. Demosaic Intel® FPGA IP 24. FIR Filter Intel® FPGA IP 25. Frame Cleaner Intel® FPGA IP 26. Full-Raster to Clocked Video Converter Intel® FPGA IP 27. Full-Raster to Streaming Converter Intel® FPGA IP 28. Genlock Controller Intel® FPGA IP 29. Generic Crosspoint Intel® FPGA IP 30. Genlock Signal Router Intel® FPGA IP 31. Guard Bands Intel® FPGA IP 32. Histogram Statistics Intel® FPGA IP 33. Interlacer Intel® FPGA IP 34. Mixer Intel® FPGA IP 35. Pixels in Parallel Converter Intel® FPGA IP 36. Scaler Intel® FPGA IP 37. Stream Cleaner Intel® FPGA IP 38. Switch Intel® FPGA IP 39. Tone Mapping Operator Intel® FPGA IP 40. Test Pattern Generator Intel® FPGA IP 41. Unsharp Mask Intel® FPGA IP 42. Video and Vision Monitor Intel FPGA IP 43. Video Frame Buffer Intel® FPGA IP 44. Video Frame Reader Intel FPGA IP 45. Video Frame Writer Intel FPGA IP 46. Video Streaming FIFO Intel® FPGA IP 47. Video Timing Generator Intel® FPGA IP 48. Vignette Correction Intel® FPGA IP 49. Warp Intel® FPGA IP 50. White Balance Correction Intel® FPGA IP 51. White Balance Statistics Intel® FPGA IP 52. Design Security 53. Document Revision History for Video and Vision Processing Suite User Guide

18.2. Clocked Video to Full-Raster Converter Parameters

Table 241.  Main Parameters
Parameter Values Description
Video Data Format
CV Bus Style Lite, CVI or CVO

Select which sideband signals the IP drives, and which signals are available in Platform Designer.

A second tab allows you to parameterize the CV bus style.

Bits per color sample 6 to 16 Number of bits per color sample.
Number of color planes 1 to 4 Number of color planes in a pixel.
Number of pixels in parallel 1, 2, 4 or 8 Number of pixels transmitted every clock.
AXI4S FR Bus has tReady connection True or False

Select true so the streaming full-raster interface contains the AXI4-S tReady signal.

Select false to remove, the tReady signal.

Control Settings
Memory-mapped control interface True or False Select True to turn on the CPU interface and associated signals. Select False to remove the CPU interface and for all the CPU registers to use default values.
Separate clock for control interface True or False

Select True to include the signal cpu_clock in Platform Designer. It is asynchronous to the video domain.

Select False so the CPU interface uses the signal vid_clock.

Dimensions
Max full-raster width 1 to 65535 The maximum width of raster that this IP passes.
Max full-raster height 1 to 65535 The maximum height of raster this IP passes.
Default full-raster width 1 to 65535

The width of the raster.

The CPU can override this value.

Default full-raster height 1 to 65535

The height of the raster.

The CPU can override this value.

Default Vsync H 1 to 65535

The default pixel position of the rising edge of the vertical timing signal (vsync or vblank)

The CPU can override this value.

Default Vsync V 1 to 65535

The default line where the rising edge of the vertical timing signal (vsync or vblank) occurs.

The CPU can override this value.

Figure 36. Main Parameters
Table 242.  CV Lite Parameters
Parameter Values Description
Parameters
Valid signal On or off When you select Lite the IP includes an optional data valid input signal, cv_vid_in_valid. Turn on to turn on this input in the IP. Platform Designer includes or removes the signal from the cv_vid_in conduit as appropriate.
Ready signal On or off When you select Lite the IP includes an optional data ready output signal, cv_vid_in_ready. Turn on to turn on this output in the IP. Platform Designer includes or removes the signal from the cv_vid_in conduit as appropriate.
Timing Signals sync, blank, or both Select which timing are available. Platform Designer includes or removes the signals from the cv_vid_in conduit as appropriate
Figure 37. CV Lite Parameters
Table 243.  CVI Parameters
Parameters Values Description
CVI Core Parameters
Source for total resolution Use Extra Logic or Use External Signals

The IP requires the height and width of the raster. Determine this information using additional logic within the IP, or get the information from optional input signals.

This parameter selects the source for the raster dimensions. Platform Designer includes or removes the signals from the cv_vid_in conduit as appropriate

CVI Legacy Tie Offs
Include the vid_hd_sdn signal True or False Select True to add this signal to the cv_vid_in conduit. The signal has no function within the IP and is included for connectivity within Platform Designer.
Include the vid_std signal True or False Select True to add this signal to the cv_vid_in conduit. The signal has no function within the IP and is included for connectivity within Platform Designer.
Width of vid_std 1 to 16 The width of the vid_std signal.
Include the hdmi_duplication signal True or False Select True to add this signal to the cv_vid_in conduit. The signal has no function within the IP and is included for connectivity within Platform Designer.
Figure 38. CVI Parameters
Table 244.  CVO Parameters
Parameters Values Description
CVO Legacy Tie Offs
Drive CV Output Clock True or False Select True to add this signal to the cv_vid_in conduit. The signal has no function within the IP and is included for connectivity within Platform Designer.
Include the underflow signal True or False Select True to add this signal to the cv_vid_in conduit. The signal has no function within the IP and is included for connectivity within Platform Designer.
Include the vid_mode_change signal True or False Select True to add this signal to the cv_vid_in conduit. The signal has no function within the IP and is included for connectivity within Platform Designer.
Include the frame lock signals True or False Select True to add this signal to the cv_vid_in conduit. The signal has no function within the IP and is included for connectivity within Platform Designer.
Include the vid_std signal True or False Select True to add this signal to the cv_vid_in conduit. The signal has no function within the IP and is included for connectivity within Platform Designer.
Width of vid_std 1 to 16 Select the width of the vid_std signal.
Figure 39. CVO Parameters