Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/31/2023
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Space Converter Intel® FPGA IP 21. Defective Pixel Correction Intel® FPGA IP 22. Deinterlacer Intel® FPGA IP 23. Demosaic Intel® FPGA IP 24. FIR Filter Intel® FPGA IP 25. Frame Cleaner Intel® FPGA IP 26. Full-Raster to Clocked Video Converter Intel® FPGA IP 27. Full-Raster to Streaming Converter Intel® FPGA IP 28. Genlock Controller Intel® FPGA IP 29. Generic Crosspoint Intel® FPGA IP 30. Genlock Signal Router Intel® FPGA IP 31. Guard Bands Intel® FPGA IP 32. Histogram Statistics Intel® FPGA IP 33. Interlacer Intel® FPGA IP 34. Mixer Intel® FPGA IP 35. Pixels in Parallel Converter Intel® FPGA IP 36. Scaler Intel® FPGA IP 37. Stream Cleaner Intel® FPGA IP 38. Switch Intel® FPGA IP 39. Tone Mapping Operator Intel® FPGA IP 40. Test Pattern Generator Intel® FPGA IP 41. Unsharp Mask Intel® FPGA IP 42. Video and Vision Monitor Intel FPGA IP 43. Video Frame Buffer Intel® FPGA IP 44. Video Frame Reader Intel FPGA IP 45. Video Frame Writer Intel FPGA IP 46. Video Streaming FIFO Intel® FPGA IP 47. Video Timing Generator Intel® FPGA IP 48. Vignette Correction Intel® FPGA IP 49. Warp Intel® FPGA IP 50. White Balance Correction Intel® FPGA IP 51. White Balance Statistics Intel® FPGA IP 52. Design Security 53. Document Revision History for Video and Vision Processing Suite User Guide

36.1. About the Scaler

The Scaler Intel FPGA IP resizes the fields in an Intel FPGA streaming video compliant input to produce output fields of a different height and or width. The IP supports both full and lite variants of interface protocol. The scaler offers three algorithms for resizing images: nearest neighbor, bilinear and polyphase. The three algorithms offer three cost versus quality options. Nearest neighbor offers the lowest FPGA resource cost and the lowest output image quality and polyphase offers the highest quality at the highest cost.

The scaler can resize an incoming video field to produce an output field of any size, restricted only by defined minimum and maximum widths and heights. You set the desired output field width and height at runtime via the register map (if the Avalon memory-mapped control agent interface is enabled), or via fixed parameters (if the Avalon memory-mapped control agent interface is not enabled). Full variants define the input field width and height by the image info packets received at the input interface. Lite variants define the input field width and height via the register map. With defined input and output widths and heights, the scaler applies the correct horizontal and vertical scaling ratios (which may be different).

The following bounds apply to the input and output field widths.

  • Input field width must be less than or equal to the value set in the maximum input field width parameter.
  • Output field width must be less than or equal to the value set in the maximum output field width parameter
  • Output field width must be greater than or equal to the value set in the number of pixels in parallel parameter

You may also choose to turn off scaling in the horizontal or vertical directions if either is not required. In this case, the output width or height is unaltered, regardless of the settings in the register map. Also, the scaler only supports scaling for video with 4:4:4 chroma siting. Full variants assert the error flag for any of these restrictions.