Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/31/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Space Converter Intel® FPGA IP 21. Defective Pixel Correction Intel® FPGA IP 22. Deinterlacer Intel® FPGA IP 23. Demosaic Intel® FPGA IP 24. FIR Filter Intel® FPGA IP 25. Frame Cleaner Intel® FPGA IP 26. Full-Raster to Clocked Video Converter Intel® FPGA IP 27. Full-Raster to Streaming Converter Intel® FPGA IP 28. Genlock Controller Intel® FPGA IP 29. Generic Crosspoint Intel® FPGA IP 30. Genlock Signal Router Intel® FPGA IP 31. Guard Bands Intel® FPGA IP 32. Histogram Statistics Intel® FPGA IP 33. Interlacer Intel® FPGA IP 34. Mixer Intel® FPGA IP 35. Pixels in Parallel Converter Intel® FPGA IP 36. Scaler Intel® FPGA IP 37. Stream Cleaner Intel® FPGA IP 38. Switch Intel® FPGA IP 39. Tone Mapping Operator Intel® FPGA IP 40. Test Pattern Generator Intel® FPGA IP 41. Unsharp Mask Intel® FPGA IP 42. Video and Vision Monitor Intel FPGA IP 43. Video Frame Buffer Intel® FPGA IP 44. Video Frame Reader Intel FPGA IP 45. Video Frame Writer Intel FPGA IP 46. Video Streaming FIFO Intel® FPGA IP 47. Video Timing Generator Intel® FPGA IP 48. Vignette Correction Intel® FPGA IP 49. Warp Intel® FPGA IP 50. White Balance Correction Intel® FPGA IP 51. White Balance Statistics Intel® FPGA IP 52. Design Security 53. Document Revision History for Video and Vision Processing Suite User Guide

21.4. Defective Pixel Correction IP Registers

Each register is either read-only (RO) or read-write (RW).

In the software API the register names appear with a prefix of INTEL_VVP, INTEL_VVP_CORE or INTEL_VVP_DPC as appropriate and with an optional REG suffix

Table 320.  Defective Pixel Correction Registers
Address Register Access Description
Lite 55 Full
Parameterization registers
0x0000 VID_PID RO N/A

Read this register to retrieve the ID of the Defective Pixel Correction IP.

This register always returns 0x6FA7_0175.

0x0004 VERSION RO N/A Read this register to retrieve the version information for the Defective Pixel Correction IP.
0x0008 LITE_MODE RO N/A

Read this register to determine if Lite mode is on.

This register always returns 1.

0x000c DEBUG_ENABLED RO N/A

Read this register to determine if Debug features are on.

This register returns 0 for off and 1 for on.

0x0010 BPS_IN RO N/A Read this register to determine the bits per symbol for the input data.
0x0014 BPS_OUT RO N/A Read this register to determine the bits per symbol for the output data.
0x0018 NUM_COLOR_IN RO N/A

Read this register to determine the number of color planes for the input data.

This register always returns 1.

0x001c NUM_COLOR_OUT RO N/A

Read this register to determine the number of color planes for the output data.

This register always returns 1.

0x0020 PIP RO N/A Read this register to determine the number of pixels in parallel.
0x0024 MAX_WIDTH RO N/A Read this register to determine the maximum supported input field width.
0x0028 MAX_HEIGHT RO N/A Read this register to determine the maximum supported input field height.
0x002c to 0x011F - - - Reserved
Control, debug, and statistics registers
0x0120 IMG_INFO_WIDTH RW N/A The expected width of the incoming video fields.
0x0124 IMG_INFO_HEIGHT RW N/A The expected height of the incoming video fields.
0x0128 to 0x013F - - - Reserved
0x0140 STATUS RO N/A

Read this register for information about the IP status.

0x0144 FRAME_STATS RO N/A

Read this register for some frame statistics.

0x0148 PIX_LO_COUNTER RO N/A

For the selected parallel pixel pipeline, read this register for the current count of pixels that have been clipped to the low value set via the sensitivity setting.

0x014c PIX_HI_COUNTER RO N/A For the selected parallel pixel pipeline, read this register for the current count of pixels that have been clipped to the high value set via the sensitivity setting.
0x0150 - - - Reserved
0x0154 CONTROL RW N/A

Control bits and fields of Defective Pixel Correction IP

0x0158 to 0x01FF - - - Reserved

Regsiter Bit Descriptions

Table 321.   STATUS
Name Bits Description
Reserved 31:3 Reserved.
Stats are Frozen 2 IP sets this bit to indicate it stopped updating the frame statistics and low and high pixel counters.
Reserved 1 Reserved.
Running 0 When 1, the IP is processing data.
Table 322.   FRAME_STATS
Name Bits Description
Reserved 31:8 Reserved..
Checksum 7:0 A simple checksum of the frame.
Table 323.   CONTROL
Name Bits Description
Freeze Stats Request 31 Allows atomic access across all statistics registers. When set, the IP updates the frame statistics and low and high pixel counters at the next frame boundary. Raise stats are frozen flag in the status register. The statistics remain unchanged until this bit is cleared.
Reserved 30:9 Write 0.
PIP clip counter selection 8:6 Specifies which pixels in parallel pipelines the IP maps to the low and high pixel counters.
Clip counter reset 5 Set to reset high and low clip counters across all pixels in parallel pipelines. Clear to enable counters.
Sensitivity level 4:3 Specifies how strong the correction factor is:
  • 00: Very weak
  • 01: Weak
  • 10: Strong
  • 11: Very strong
Color filter array phase. 2:1 Specifies 2x2 color filter order starting from the top left corner of the image.
00 01 10 11
RG GR GB BG 
GB BG RG GR
Bypass 0 Set to bypass the Defective Pixel Correction IP. When set, the IP passes the input image unmodified.
55 Registers are RW only if you also turn on Debug features, otherwise they are WO.