Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 12/31/2023
Public

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Document Table of Contents
1. About the Video and Vision Processing Suite 2. Getting Started with the Video and Vision Processing IPs 3. Video and Vision Processing IPs Functional Description 4. Video and Vision Processing IP Interfaces 5. Video and Vision Processing IP Registers 6. Video and Vision Processing IPs Software Programming Model 7. Protocol Converter Intel® FPGA IP 8. 1D LUT Intel® FPGA IP 9. 3D LUT Intel® FPGA IP 10. AXI-Stream Broadcaster Intel® FPGA IP 11. Bits per Color Sample Adapter Intel FPGA IP 12. Black Level Correction Intel® FPGA IP 13. Black Level Statistics Intel® FPGA IP 14. Chroma Key Intel® FPGA IP 15. Chroma Resampler Intel® FPGA IP 16. Clipper Intel® FPGA IP 17. Clocked Video Input Intel® FPGA IP 18. Clocked Video to Full-Raster Converter Intel® FPGA IP 19. Clocked Video Output Intel® FPGA IP 20. Color Space Converter Intel® FPGA IP 21. Defective Pixel Correction Intel® FPGA IP 22. Deinterlacer Intel® FPGA IP 23. Demosaic Intel® FPGA IP 24. FIR Filter Intel® FPGA IP 25. Frame Cleaner Intel® FPGA IP 26. Full-Raster to Clocked Video Converter Intel® FPGA IP 27. Full-Raster to Streaming Converter Intel® FPGA IP 28. Genlock Controller Intel® FPGA IP 29. Generic Crosspoint Intel® FPGA IP 30. Genlock Signal Router Intel® FPGA IP 31. Guard Bands Intel® FPGA IP 32. Histogram Statistics Intel® FPGA IP 33. Interlacer Intel® FPGA IP 34. Mixer Intel® FPGA IP 35. Pixels in Parallel Converter Intel® FPGA IP 36. Scaler Intel® FPGA IP 37. Stream Cleaner Intel® FPGA IP 38. Switch Intel® FPGA IP 39. Tone Mapping Operator Intel® FPGA IP 40. Test Pattern Generator Intel® FPGA IP 41. Unsharp Mask Intel® FPGA IP 42. Video and Vision Monitor Intel FPGA IP 43. Video Frame Buffer Intel® FPGA IP 44. Video Frame Reader Intel FPGA IP 45. Video Frame Writer Intel FPGA IP 46. Video Streaming FIFO Intel® FPGA IP 47. Video Timing Generator Intel® FPGA IP 48. Vignette Correction Intel® FPGA IP 49. Warp Intel® FPGA IP 50. White Balance Correction Intel® FPGA IP 51. White Balance Statistics Intel® FPGA IP 52. Design Security 53. Document Revision History for Video and Vision Processing Suite User Guide

51.4. White Balance Statistics IP Registers

Each register is either read-only (RO) or read-write (RW).
Table 1004.  White Balance Statistics IP Registers

In the software API the register names appear with a prefix of INTEL_VVP, INTEL_VVP_CORE, or INTEL_VVP_WBS as appropriate and with an optional REG suffix

Address Register Access Description
Lite 156 Full
Parameterization registers
0x0000 VID_PID RO N/A

Read this register to retrieve the ID of the IP.

This register always returns 0x6FA7_0179.

0x0004 VERSION RO N/A Read this register to retrieve the version information for the IP.
0x0008 LITE_MODE RO N/A

Read this register to determine if Lite mode is on.

This register always returns 1.

0x000C DEBUG_ENABLED RO N/A

Read this register to determine if Debug features are on.

This register returns 0 for off and 1 for on.

0x0010 BPS_IN RO N/A Read this register to determine the Bits per color symbol for the input streaming video interface.
0x0014 BPS_OUT RO N/A

Read this register to determine the Bits per color symbol for the output streaming video interface.

The value of this register reads the same for its input counterpart.

0x0018 NUM_COLOR_IN RO N/A Read this register to determine the Number of color planesfor the input streaming video interface.
0x001C NUM_COLOR_OUT RO N/A

Read this register to determine the Number of color planesfor the output streaming video interface.

The value of this register reads the same for its input counterpart.

0x0020 PIP RO N/A Read this register to determine the Number of pixels in parallel.
0x0024 MAX_WIDTH RO N/A Read this register to determine the Maximum field width.
0x0028 MAX_HEIGHT RO N/A Read this register to determine the Maximum field height.
0x002C PRECISION_BITS RO N/A Read this register to determine the Number of internal fixed point precision bits.
0x0030 to 0x011F - - - Reserved.
Control, debugging, and statistics registers
0x0120 IMG_INFO_WIDTH RW N/A The expected width of the incoming video fields.
0x0124 IMG_INFO_HEIGHT RW N/A The expected height of the incoming video fields.
0x0128 to 0x013F - - - Reserved.
0x0140 STATUS RO N/A

Read this register for information about the IP status.

0x0144 FRAME_STATS RO N/A

Read this register for some frame statistics.

0x01 48

COMMIT RW N/A

Write any value to this register to submit changes to the control, region of interest, zone and range registers.

A pending commit request does not block Freeze Statistics Request of the CONTROL register, which the IP samples continuously.

0x014C CONTROL RW N/A

Control bits and fields of the IP.

0x0150 H_START RW N/A Region of interest horizontal start value
0x0154 V_START RW N/A Region of interest vertical start value
0x0158 H_END RW N/A Region of interest horizontal end value
0x015C V_END RW N/A Region of interest vertical end value
0x0160 ZONE_H_COUNT RW N/A Zone horizontal count value
0x0164 ZONE_V_COUNT RW N/A Zone vertical count value
0x0168 CFA_X0_RANGE_LO RW N/A Low range value for the left column of the color filter array.
0x016c CFA_X0_RANGE_HI RW N/A High range value for the left column of the color filter array.
0x0170 CFA_X1_RANGE_LO RW N/A Low range value for the right column of the color filter array.
0x0174 CFA_X1_RANGE_HI RW N/A High range value for the right column of the color filter array.
0x0178 to 0x01FF - - - Reserved
0x0200 – 0x09FC RESULTS_TABLE RO N/A White balance statistics values
0x0A00 to 0x0FFF - - - Reserved

Register Bit Descriptions

Table 1005.   STATUS
Name Bits Description
Reserved 31:3 Reserved.
Stats are Frozen 2 The IP sets this bit to indicate it stopped updating the statistics.
Commit 1 Pending commit
Running 0 When 1 the IP is processing data.
Table 1006.   FRAME_STATS
Name Bits Description
Reserved 31:8 Reserved.
Checksum 7:0 A simple checksum of the frame.
Table 1007.   CONTROL
Name Bits Description
Freeze Statistics Request 31 Set this bit to 1 for the IP to start sampling a new set of white balance and frame statistics. The IP lowers the Stats are Frozen bit of the STATUS register as a response, and you need to poll Stats are Frozen bit until it is 1 before reding the statistics. You should keep Freeze Statistics Request 1 until it raises Stats are Frozen. You must set Freeze Statistics Request to 0 before starting over with a new sampling request. Deviating from this flow might result in unexpected IP behavior.
Reserved 30:5 Reserved.
Color filter array phase invert 4:3

Independently invert the numerator and denominator pixels of the 2x2 CFA phase. For example, if color filter array phase is 00, and color filter array phase invert is 01, the effective color filter array phase is:

C0C3 
C2C1 

Likewise, when color filter array phase invert is 10:

C2C1
C0C3
Color filter array phase 2:1 Specifies 2x2 color filter order starting from the top left corner of the image.
 00  01   10  11
C0C1 C1C0 C2C3 C3C2
C2C3 C3C2 C0C1 C1C0
Reserved 0 Reserved. Write 0.
Table 1008.   H_START
Name Bits Description
Reserved 31:16 Reserved. Write 0.
Position 15:0 Horizontal position of the first pixel in the region of interest. The IP starts counting the pixels from index 0. Set the value of this register to a number that is even and an integer multiple of Number of pixels in parallel.
Table 1009.   V_START
Name Bits Description
Reserved 31:16 Reserved. Write 0.
Position 15:0

Vertical position of the first line in the region of interest. The IP starts counts the lines from index 0. Set the value of this register to an even number.

.
Table 1010.   H_END
Name Bits Description
Reserved 31:16 Reserved. Write 0.
Position 15:0

Horizontal position of the last pixel in the region of interest incremented by 1. The horizontal size of the region of interest must be even and an integer multiple of Number of pixels in parallel. Therefore, set the value of this register to an odd number and an integer multiple of Number of pixels in parallel incremented by 1.

Table 1011.   V_END
Name Bits Description
Reserved 31:16 Reserved. Write 0.
Position 15:0

Vertical position of the last line in the region of interest incremented by 1. The vertical size of the region of interest must be even. Therefore, set the value of this register to an odd number.

Table 1012.   ZONE_H_COUNT
Name Bits Description
Reserved 31:16 Reserved. Write 0.
Value 15:0 Number of horizontal pixels in a zone. Set the value of this register to an even number.
Table 1013.   ZONE_V_COUNT
Name Bits Description
Reserved 31:16 Reserved. Write 0.
Value 15:0 Number of vertical pixels in a zone. Set the value of this register to an even number.
Table 1014.   CFA_X0_RANGE_LO
Name Bits Description
Value 31:0 Lower range of the ratio check for the left column of the 2x2 color filter array. The IP marks the whole 2x2 color filter array out of range and discards all statistics regarding the 2x2 pixel group if the ratio calculated for the left column of the 2x2 color filter array is smaller than the value of this register. 157
Table 1015.   CFA_X0_RANGE_HI
Name Bits Description
Value 31:0 Higher range of the ratio check for the left column of the 2x2 color filter array. The IP marks the whole 2x2 color filter array out of range and discards all statistics regarding the 2x2 pixel group if the ratio calculated for the left column of the 2x2 color filter array is greater than the value of this register.157
Table 1016.   CFA_X1_RANGE_LO
Name Bits Description
Value 31:0 Lower range of the ratio check for the right column of the 2x2 color filter array. The IP marks the whole 2x2 color filter array out of range and discards all statistics regarding the 2x2 pixel group if the ratio calculated for the right column of the 2x2 color filter array is smaller than the value of this register.157
Table 1017.   CFA_X1_RANGE_HI
Name Bits Description
Value 31:0 Higher range of the ratio check for the right column of the 2x2 color filter array. The IP marks the whole 2x2 color filter array out of range and discards all statistics regarding the 2x2 pixel group if the ratio calculated for the right column of the 2x2 color filter array is greater than the value of this register.157
Table 1018.   RESULTS_TABLE
Name Bits Description
Reserved 31:20 Reserved.
White balance statistics values. 19:0

The IP stores the statistics for each zone linearly from zone 1 to zone 49, packing 7x7 zones in raster order, left to right, top to bottom. The IP concatenates the two sum of ratios and the number of counted 2x2 color filter arrays, spanning across multiple registers. Intel provides an API function for reading statistics using zone coordinates and unpacking the statistics into a more accessible form.

156 Registers are RW only if you also turn on Debug features, otherwise they are WO.
157 The numbering format is fixed-point unsigned integer 16.16, where the bit ranges [31:16] and [15:0] are the integer and fractional parts, respectively. For the integer part, the IP uses the least significant Bits per color sample number of bits and assumes the remaining MSBs are 0. For the fractional part, the IP uses the most significant Number of internal fixed point precision bits and assumes the remaining LSBs are 0.